Implementation and Characterization of an Integrate-and-Fire Neuron Circuit Using a Silicon Nanowire Feedback Field-Effect Transistor

Woo, Sola; Cho, Jinsun; Lim, Doohyeok; Park, Young-Soo; Cho, Kyoungah

doi:10.1109/ted.2020.2995785

Cited by 21 publications

(14 citation statements)

References 23 publications

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“…In Table 1 , the CMOS, floating-gate FET and FBFET neuron circuits reported by other research groups require 5–23 elements with capacitors, and more than 1–10 external bias lines which require extra peripheral circuit for generating bias voltages, causing these neuron circuits to consume high power and energy ( Indiveri et al, 2006 ; Kornijcuk et al, 2016 ; Choi et al, 2018 ; Kwon et al, 2018 ; Kim et al, 2019 ; Wang and Khan, 2019 ; Zhang and Wijekoon, 2019 ; Chavan et al, 2020 ; Woo et al, 2020 ). The FBFET neuron circuit has relatively low energy consumption compared to others except ours, but this neuron circuit requires extra peripheral circuits for generating voltage bias and controllers for the I&F operation ( Choi et al, 2018 ; Kwon et al, 2018 ; Woo et al, 2020 ). The PDSOI MOS-based neuron circuit also requires an external reset circuit applied with changeable gate voltage to reset the membrane potential ( Chavan et al, 2020 ).…”

Section: Proposed Iandf Neuron Circuitmentioning

confidence: 99%

“…Despite their advantages over Von-Neumann computing architectures in terms of energy efficiency, neuron circuits, driven by spiking neural networks (SNNs), still need more power for their integrate-and-fire (I&F) operations than biological neurons ( Choi et al, 2018 ). For most neuron circuits, particularly those using complementary metal-oxide semiconductor (CMOS), feedback field-effect-transistor (FBFET), and floating gate FET (FGFET) ( Indiveri et al, 2006 ; Kornijcuk et al, 2016 ; Choi et al, 2018 ; Kwon et al, 2018 ; Kim et al, 2019 ; Wang and Khan, 2019 ; Zhang and Wijekoon, 2019 ; Chavan et al, 2020 ; Woo et al, 2020 ), the presence of numerous transistors and external bias lines result in relatively high power consumption for the I&F operations. Thus, for energy-efficient neuron circuits, suppression in numbers of transistors, absence of external bias lines, and use of steep switching devices with extremely low subthreshold swings ( SS s) are needed ( Abbott, 1999 ; Izhikevich, 2003 ; Cheung, 2010 ); the steep switching devices are crucially necessary for a substantial reduction in power consumption of neuron circuits.…”

Section: Introductionmentioning

confidence: 99%

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Integrate-and-Fire Neuron Circuit Without External Bias Voltages

et al. 2021

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In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

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Section: Proposed Iandf Neuron Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Integrate-and-Fire Neuron Circuit Without External Bias Voltages

et al. 2021

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“…The small mismatches in the parameter fitting result occurred due to the limitation of the models, as described in Section 3.1. Figure 8a shows the circuit diagram of an integrate and fire (I&F) circuit for a spiking neural network (SNN) [21]. Complementary MOS (CMOS)-based I&F circuits have a number of MOSFETs for implementing spike and reset mechanisms; therefore the circuits have a high power consumption.…”

Section: Model Validationmentioning

confidence: 99%

“…The electrical characteristics of the FBFET have been investigated using the FBFET as a logic gate [10][11][12][13][14][15][16]. In addition, memory circuits, neuromorphic circuits, and biosensors consisting of FBFETs or hybrid components (e.g., the FBFET and the MOSFET) were investigated utilizing charging in the channel region and the hysteresis characteristics [17][18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

2021

Micromachines

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In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement IDS-VGS characteristics but could not accurately implement IDS-VDS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the IDS-VGS characteristics but also the IDS-VDS characteristics. A hybrid inverter and an integrate and fire (I&F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

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“…Therefore, it can be used as a logic and memory device with the same structure. Various applications of FBFET were studied, such as using it as a logic device, a memory device, and a neuron circuit [ 24 , 25 , 26 , 27 , 28 , 29 , 30 ]. In the previous study, we investigated electrical coupling between vertically stacked FBFETs in the monolithic 3-dimensional inverter (M3DINV) with FBFETs, in terms of device characteristics [ 31 ].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

2020

Micromachines

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The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

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Implementation and Characterization of an Integrate-and-Fire Neuron Circuit Using a Silicon Nanowire Feedback Field-Effect Transistor

Cited by 21 publications

References 23 publications

Integrate-and-Fire Neuron Circuit Without External Bias Voltages

Integrate-and-Fire Neuron Circuit Without External Bias Voltages

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

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