Impacts of Uniaxial Compressive Strain on Dynamic Negative Bias Temperature Instability of p-Channel MOSFETs

Abstract

Dynamic negative bias temperature instability ͑DNBTI͒ characteristics of p-metal oxide semiconductor field-effect transistors ͑p-MOSFETs͒ with compressive channel strain induced by a SiN-capping layer were investigated. Although the SiN-capping is effective in boosting the device drive current, it may concomitantly worsen DNBTI characteristics. This is ascribed to higher hydrogen content incorporated during SiN deposition as well as higher strain energy stored in the channel. A strong dependence on the ac stress frequency is also observed for the SiN-capped devices, which is ascribed to excess hydrogen species contained in the strained devices. Finally, our experimental results also suggest that the aggravated NBTI in the strained devices could be alleviated by high frequency operation.With the scaling of metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒, the carrier mobility is severely degraded due to the higher channel doping necessary for keeping the short-channel effects at bay. Recently, mobility enhancement by channel strain engineering has emerged as the most effective approach to alleviate the above restriction. 1-7 Among the plethora of methods proposed, the use of a SiN capping layer deposited by plasma-enhanced chemical vapor deposition ͑PECVD͒ is very attractive for introducing a compressive strain to the channel of p-MOSFETs suitable for ultralarge scale integrated ͑ULSI͒ manufacturing. 3,4 Although the strained channel could enhance the mobility and thus the drive current of the device, potentially it could concomitantly compromise the device's reliability characteristics owing to strained energy contained in the channel and the processing steps needed to form the strain booster structure. Conventionally, characterization of negative bias temperature instability ͑NBTI͒ is primarily based on static experimental data. However, for real-life operations of digital circuits, the applied bias to the gate of p-MOSFETs in a complementary metal oxide semiconductor ͑CMOS͒ inverter is being switched between high and low voltages incessantly. During the low phase of p-MOSFETs bias, the electric passivation effect may effectively reduce the interface traps generated during the high phase operation. The dynamic NBTI ͑DNBTI͒ effect greatly prolongs the lifetime of p-MOSFETs operating in a practical digital circuit, 8 while the conventional static NBTI measurement could severely underestimate the p-MOSFET lifetime. Furthermore, the DNBTI effect is dependent on both the temperature and gate oxide thickness. 8 A physical model has been previously proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds. 9 According to this reaction-diffusion theory, the threshold voltage shift ͑⌬V th ͒ is attributed to the creation of interface traps as a consequence of dissociation of the Si-H bonds, and subsequent diffusion of the released hydrogen species towards the gate electrode. In the recovery process, released hydrogen repassivates Si dangling bonds. 9 In this work, we investig...

Carrier Mobility Characteristics and Negative Bias Temperature Instability Reliability in Strained-Si p-Type Metal-Oxide-Semiconductor Field-Effect Transistors

“…4,5 Recently, it has been shown that NBTI-induced degradation was more severe in strained-Si p-MOSFETs. 6 Our observation indicates that there is a trade-off between device performance and reliability, i.e., a higher enhancement of mobility may adversely degrade the device reliability. Until now, only a few studies 7 have been done on the reliability investigation of these devices, such that this trade-off is unknown.…”

Reliability of HfSiON gate dielectric silicon MOS devices under [110] mechanical stress: Time dependent dielectric breakdown

“…6͑b͒ and 6͑c͒, 24 both ͓110͔ tensile and compressive mechanical stresses may degrade NBTI in high-k Si MOSFETs. 6,30 As discussed above, positive BTI ͑PBTI͒ may not generate interface traps but may instead involve charge trapping in high-k bulk or high-k / Si interface. 16,29 This may result in improved PBTI via mechanical stress-induced increase in charge detrapping in thick ͑Ͼ7 nm͒ HfO 2 Si MOSFET.…”

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

“…However, the NBTI instability of strained devices could be alleviated by operating at high frequency. 64 The excess hydrogen content within SiN CESLs can also lead to increased substrate current and potentially aggravate hot-electron effects. The deposition of a tetraethyl orthosilicate (TEOS) buffer layer prior to that of a SiN CESL could block the diffusion of hydrogen and thus improve the hotelectron reliability.…”