Carrier Mobility Characteristics and Negative Bias Temperature Instability Reliability in Strained-Si p-Type Metal-Oxide-Semiconductor Field-Effect Transistors

Abstract

Surface-channel p-type metal-oxide-semiconductor field-effect transistors ͑pMOSFETs͒ processed on the strained-Si/relaxed-SiGe substrate feature significantly enhanced hole mobility ͑45%͒ compared to the unstrained-Si control device. Analysis of the mobility characteristics shows that surface roughness scattering for strained-Si pMOSFETs begins to dominate at a relatively low effective field ͑ϳ0.1 MV/cm͒ and thus limits the drive current enhancement. In addition, experimental data indicate that negative bias temperature instability is a potential reliability concern for strained-Si pMOSFETs.The dimensions of complementary metal-oxide-semiconductor ͑CMOS͒ devices have been continually shrunk to attain greater packing density, higher power dissipation, and higher drive current. Drive current enhancement may also be achieved by increasing the carrier mobility in the channel. Reports have shown that the strained-Si/SiGe heterostructure metal-oxide-semiconductor fieldeffect transistor ͑MOSFET͒ is a promising device structure for sub-0.1 m high-speed CMOS technology because of its high electron and hole mobilities. 1,2 The biaxial tension in strained Si modifies the band structure of Si and enhances carrier transport due to suppressed intervalley phonon scattering and reduced in-plane effective mass. 3 However, as the feature sizes of Si MOSFET devices are scaled into the nanometer regime, negative bias temperature instability ͑NBTI͒ degradation continues to be an important device design constraint. NBTI gives rise to an increase of threshold voltage and decrease of the drive current of a transistor due to the buildup of positive charge and interface states in the gate oxide. 4,5 Recently, it has been shown that NBTI-induced degradation was more severe in strained-Si p-MOSFETs. 6 Our observation indicates that there is a trade-off between device performance and reliability, i.e., a higher enhancement of mobility may adversely degrade the device reliability. Until now, only a few studies 7 have been done on the reliability investigation of these devices, such that this trade-off is unknown. In this article, we have studied the drain current ͑in-cluding subthreshold slope, drain-induced barrier lowering, and offleakage current͒, carrier mobility characteristics, and NBTI reliability in short channel strained-Si pMOSFETs. ExperimentalThe heterostructure was grown by ultrahigh vacuum chemical vapor deposition ͑UHVCVD͒ on a p + ͑boron-doped 10 19 cm −3 ͒ Si handle wafer. It is comprised of a 2 m compositionally graded buffer followed by a 3.5 m relaxed p-type Si 0.7 Ge 0.3 layer and 20 nm strained-Si layer on top. A Si 1−x Ge x graded layer was employed to minimize the formation of threading dislocations. The strained-and unstrained-Si ͑control sample͒ devices were simultaneously processed using a standard 0.13 m CMOS fabrication technique. All samples were grown on oxynitride film with a thickness of 16 Å in a rapid thermal annealing ͑RTA͒. Then, a poly-Si film of 175 nm was deposited and BF 2 implanted. TEOS deposition an...

Method of estimating mechanical stress on Si body of MOSFET using drain–body junction current

“…Also, σ affects the degradation of MOSFETs due to electrical stresses such as hot carrier injection and bias temperature instability. [12][13][14][15][16][17][18] Two electrical methods of estimating σ on the Si substrate of MOSFETs have been proposed; one uses a change in μ due to σ 2,19) and the other uses a change in the subthreshold current I d(sub) . 20,21) The method of using μ measures the difference Δμ in μ between a stress-free reference MOSFET and a stressed measurement MOSFET, and then uses the fact that Δρ=ρ ≈ −Δμ=μ, where ρ ∝ 1=μ is the resistivity, and estimates σ by dividing −Δμ=μ by the effective piezoresistive coefficient 22) in the direction of the channel.…”