Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack

On the validity and applicability of models of negative capacitance and implications for MOS applications

“…Switching kinetics for HfO 2 -based FE (used extensively in device studies) was measured for scaled devices (80 nm width and 30 nm length) 19 finding that switching is quite slow, with time constants of ∼ ms-µs at voltages of 2-3 V for 10 nm films 19 . We attribute the small or apparent lack of hysteresis observed in some experiments (considered as supporting evidence of NS models) to canceling between the counter-clockwise (CCW) FE and the clockwise (CW) charge trapping-detrapping hysteresis (See examples in Fig.2, measured on samples fabricated following experimental details given in 16,17 ). The implications of the stabilized NS QSNC model vs. those of FE switchingbased models for sub-60 mV/dec SS MOS applications are significantly different.…”

“…This reasoning suggests the possibility of stabilized QSNC in MOS devices with a FE layer in the gate stack. Note, however, that even if the channel and the FE layer would have the same polarization, this would not lead to a sub-60 mV/dec SS as observed in devices with DE IL/HfO 2based FE bi-layers in the gate stack 16,17 ; rather, it would lead to the channel and FE having similar dielectric-like behavior with the same permittivity (both having positive capacitance), which does not lead to sub-60 mV/dec SS. In any case, there is no general physical foundation for assuming the polarizations to be the same in all situations.…”

“…The occurrence of stabilized quasi-static (QS) negative capacitance (NC) in systems that include ferroelectric (FE) layers has recently been postulated [1][2][3][4] and been the subject of many studies [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] . The observation of room temperature sub-60 mV/dec sub-threshold slope (SS) for MOSFET devices that included FE layers in the gate stack or in series with the gate [5][6][7]16,17 has triggered significant interest due to potential applications in low power CMOS. Observation of sub-60 mV/dec SS [5][6][7] or improvements of SS 8,9 have been regarded as supporting evidence for models of stabilized QSNC [1][2][3][4][5]8,[10][11][12][13][14][15] .…”

ZrO2 Negtive Capacitance Field-Effect Transistor with Sub-60 Subthreshold Swing Behavior

“…compares the measured gate leakage I G -V GS curves for the 5 nm Al 2 O 3 /HfO 2 NCFET at the V DS of -0.05 V and -0.5 V.The sudden drops of I G onlyduring the reverse sweeping indicate the decreased voltage in the amorphous HfO 2 lm and the amplication of surface potential[43]. The absence of NC effect during the forward sweeping is caused by the partical switching of oxygen vacancy dipoles in the amorphous HfO 2 lm[44].The different ability to contain oxygen atoms between Al 2 O 3 and HfO 2 layer leads to oxygen redistribution and negative interfacial dipoles at the Al 2 O 3 /HfO 2 interface[45][46][47]. Due to the presense of negative interfacial dipoles, it is di cult for the amorphous HfO 2 lm to realize complete polarization swiching (NC effect) in the forward sweeping.…”

Improved Negative‐Capacitance Switch of Ferroelectric Field Effect Transistor Using Defect Passivation Engineering

“…Figure shows the s tatistical distributions of SS min , indicating that more than ≈90% devices can achieve an energy‐efficient switch of sub‐60 mV dec −1 SS. Although the presence of residual charge may obstruct the ferroelectric dipole switching and further affects the surface potential gain of transistor during forward and reverse sweeps, the narrow SS distribution (SS avg <35 mV dec −1 ) for both forward and reverse directions verifies the NC switching stability in fluorine‐passivated HfAlO x NC FETs.…”