Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

Mercha, A.; Redolfi, A.; Stucchi, M.; Minas, Nikolaos; Olmen, J. Van; Thangaraju, Sarasvathi; Velenis, Dimitrios; Domae, S.; Yu, Yang; Katti, Guruprasad; Labie, Riet; Okoro, Chukwudi; Zhao, Ming; Asimakopoulos, Panagiotis; Wolf, Ingrid De; Chiarella, T.; Schram, T.; Röhr, E.; Ammel, A. Van; Jourdain, Anne; Ruythooren, Wouter; Armini, Silvia; Radisic, Aleksandar; Philipsen, Harold; Heylen, N.; Kostermans, M.; Jaenen, Patrick; Sleeckx, Erik; Tezcan, Deniz Sabuncuoglu; Debusschere, I.; Soussan, Philippe; Perry, D.; Plas, G. Van der; Cho, J.H.; Marchal, Pierre; Travaly, Youssef; Beyne, Eric; Biesemans, S.; Swinnen, Bart

doi:10.1109/vlsit.2010.5556190

Cited by 15 publications

(12 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The justifiable concern then, is that these stresses could adversely affect device performance. Some investigators have studied this effect, and reported their findings [26,[46][47][48][49][50].…”

Section: Tsv Impact On Devicesmentioning

confidence: 98%

“…However, Mercha et al [47] reported the impact of TSV stress on high precision analog devices using a high resolution DAC (digital analog conversion) circuit. TSV's were placed at various distances from MOS (metal oxide semiconductor) devices ranging from 1.7 to 20.7 µm, to determine the transistor 'keep-out' zones [47].…”

Section: Tsv Impact On Devicesmentioning

confidence: 99%

“…TSV's were placed at various distances from MOS (metal oxide semiconductor) devices ranging from 1.7 to 20.7 µm, to determine the transistor 'keep-out' zones [47]. The results show that the TSV's do influence the performance of the devices for particular orientations, and proximity of 2 µm or less.…”

Section: Tsv Impact On Devicesmentioning

confidence: 99%

See 2 more Smart Citations

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

show abstract

Section: Tsv Impact On Devicesmentioning

confidence: 98%

Section: Tsv Impact On Devicesmentioning

confidence: 99%

See 1 more Smart Citation

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…There is considerable interest in extreme wafer thinning for use in advanced packaging applications (including 3D integration [1]) [2,3,4]. As this emerging technology will be combined with advances in CMOS technology, it is important to understand the effects it has on the most modern and sophisticated devices available.…”

Section: Introductionmentioning

confidence: 99%

Impact of wafer thinning on High-K Metal Gate 20nm devices

Beece

Agarwal

Chandrashekhar

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100µm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature instability) measurements. It is found that wafer thinning has negligible impact on Vt of I/O devices. However, we have seen a small impact on the channel leakage, and a moderate impact on saturation currents of high performance core devices. The channel current is reduced ~5% for NMOS, while there is a ~10% enhancement in the PMOS device. Device reliability was assessed using NBTI and no degradation is seen on the devices. This confirms that the thinning did not impact the front end of line gate oxide integrity.

show abstract

“…• C) [2]. This mechanical stress can be decomposed in two directions, radial tension and tangential compression, as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Methodology for analysis of TSV stress induced transistor variation and circuit performance

Chang²,

Zuo³

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

Abstract-As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.

show abstract

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

Cited by 15 publications

References 0 publications

3D integration review

3D integration review

Impact of wafer thinning on High-K Metal Gate 20nm devices

Methodology for analysis of TSV stress induced transistor variation and circuit performance

Contact Info

Product

Resources

About