Impact of wafer thinning on High-K Metal Gate 20nm devices

Abstract

In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100µm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature instability) measurements. It is found that wafer thinning has negligible impact on Vt of I/O devices. However, we have seen a small impact on the channel leakage, and a moderate impact on saturation currents of high performance core devices. The channel current is reduced ~5% for NMOS, while there is a ~10% enhancement in the PMOS device. Device reliability was assessed using NBTI and no degradation is seen on the devices. This confirms that the thinning did not impact the front end of line gate oxide integrity.

TSV integration on 20nm logic Si: 3D assembly and reliability results

“…These parameters were measured again after the wafer thinning process to study the impact of wafer thinning on device performance. Post thinning testing was performed with thin wafers on tape frame as discussed by Adam et al [5]. The delta/difference in Vt lin and Id lin between pre-thinning and post-thinning (50µm) wafer is shown in Figure 11.…”