Impact of the H2 bake temperature on the structural properties of tensily strained Si layers on SiGe

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

“…Surfaces nevertheless remain flat irrespective of the sSi layer thickness or the Ge content of the VS underneath (root mean square roughness in-between 0.27 and 0.40 nm for Ge contents in the 20-50% range) [30][31][32]. The interfaces in-between sSi and SiGe are abrupt, as illustrated by High Resolution TEM (see Fig.…”

Smooth and high quality epitaxial strained Ge grown on SiGe strain relaxed buffers with 70–85% Ge

“…It is defined as background light scattered (absence of a point defect), measured as the fraction of the incident laser power, scattered into the channel collector, and expressed in ppm. The haze value depends on the micro-roughness of the wafer surface [19,20]. Total reflection X-ray fluorescence (TXRF) was used to study the surface contamination.…”

“…The DW configuration is most sensitive to surface roughness with a spatial wavelength in the range 0.3-1 mm. The DN configuration gives information in the range $1-3 mm [19,20]. However, the measured haze values depend on the hardware settings of the surfscan tool (e.g.…”

Epitaxy of Group-IV Semiconductors for Quantum Electronics

“…Dedicated Chemical Mechanical Polishing (CMP) steps and wet cleanings (16) help in recovering flat, featureless surfaces that are fit for re-epitaxy, as shown in Figure 5 for Si0.26Ge0.74 and Si0.21Ge0.79 VS. One should however be very much aware that the periodic strain field that gave birth to the surface cross-hatch is still present in polished SiGe VS. Using high thermal budget processes on such VS will thus result in the re-appearance of that crosshatch, although the starting surface is flat (17)(18)(19). We could have used the Reverse Linear Grading (RLG) approach pioneered by the Warwick University to obtain thick, fully relaxed and high Ge content SiGe layers on Si(001) substrates.…”