Impact of skew and jitter on the performance of VLSI interconnects

Khanna, Gargi; Chandel, Rajeevan; Chandel, Ashwani Kumar

doi:10.1109/apccas.2010.5775007

Cited by 2 publications

References 11 publications

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Mitigation techniques for crosstalk in ICs

Razif

Maharum

Hasani

et al. 2019

IOP Conf. Ser.: Mater. Sci. Eng.

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Crosstalk is a major concern among integrated circuit (IC) designers as it may contribute significantly to the amount of noise presented in a device. Hence, there is a need to mitigate the impact of crosstalk in order to preserve the signal integrity between interconnections. This paper will review several methods to mitigate crosstalk in high speed ICs. The methods include the usage of repeater, Schmitt trigger, shielding, skewing, space adjustment between signal wires and setting the coupling length of the signal wires. Although these methods are effective for crosstalk mitigation, the features might only be applicable due to certain constraints. Consequently, this paper will provide a sufficient review on each method as a guideline for crosstalk mitigation method selection in which the crosstalk is largely regulated in long interconnections.

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Mitigation techniques for crosstalk in ICs

Razif

Maharum

Hasani

et al. 2019

IOP Conf. Ser.: Mater. Sci. Eng.

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System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics

Bandiziol

Grollitsch

Brandonisio

et al. 2017

2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for a high speed serial interface to be used in automotive Electronic Control Units. The transmitter has been designed in a standard 28 nm technology and features feed-forward equalization (FFE) with 8 taps (1 pre- and 6 post-cursors), whose strength is programmable with 16 discretization steps. It is shown that the parasitic inductance on the supply terminals degrades the performance in\ud terms of jitter and SNR and tends to hamper the benefits of FFE. When the value of these inductances is minimized, system-level models of the transmitter reproduce quite well time-consuming transistor-level simulations

show abstract

Impact of skew and jitter on the performance of VLSI interconnects

Cited by 2 publications

References 11 publications

Mitigation techniques for crosstalk in ICs

Mitigation techniques for crosstalk in ICs

System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics

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