Impact of Si surface roughness on MOSFET characteristics with ultrathin HfON gate insulator formed by ECR plasma sputtering

Abstract

In this paper, the impact of Si surface roughness on metal oxide semiconductor field effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) sputtering was investigated. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.08 nm (as-cleaned: 0.21 nm). The HfON was formed by 2 nm-thick HfN deposition followed by the Ar/O 2 plasma oxidation. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reduction of Si surface roughness.

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

“…The reliability of HfON thin films was also significantly improved by the reduction of Si surface roughness. In this section, the influence of Si surface roughness on the MOSFET characteristics is described [37,38,39]. The nMOSFETs with HfON gate insulator were fabricated on p-Si(100) substrates by typical gate-last process as follows [38,39].…”

“…In this section, the influence of Si surface roughness on the MOSFET characteristics is described [37,38,39]. The nMOSFETs with HfON gate insulator were fabricated on p-Si(100) substrates by typical gate-last process as follows [38,39]. After the isolation of active region by local oxidation of Si (LOCOS) process, the channel stopper was formed below field oxide (BF 3 , 100 keV, 1 Â 10 14 cm !2 ).…”

HfN multi charge trapping layers for Hf-based metal-oxide-nitride-oxide-Si nonvolatile memory

“…The Hf-based MONOS NVM was in situ formed on p-Si(100) substrate by the gate-last process. [22][23][24][25][26][27][28] After the active region formation and channel stop ion implantation, ion implantation was carried out for source and drain (S/D) regions (PH 3 , 5 × 10 15 cm −2 , 20 keV) followed by the activation annealing at 900 °C/20 min in N 2 ambient. Then, the MONOS structure was in situ deposited on p-Si(100) by electron cyclotron resonance plasma sputtering (AFTEX 3400) at room temperature (RT).…”

Multi-level 2-bit/cell operation utilizing Hf-based metal/oxide/nitride/oxide/silicon nonvolatile memory with HfO2 and HfON tunneling layer

“…[19][20][21] Meanwhile, HfON suppresses the SiO 2 IL growth. [20][21][22][23] Therefore, Hf-based MONOS devices with HfON TL show fast-operation speed and low-voltage operation compared to HfO 2 TL by decreasing the EOT. It was realized that a memory window (MW) of 1 V was obtained even at a low program voltage and high-speed operation, such as ±8 V/100 μs which is 2000 times faster than HfO 2 TL.…”