Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics

Miyamoto, Masahiko; Ohta, Hiroyuki; Kumagai, Y.; Sonobe, Y.; Ishibashi, K.; Tainaka, Yasushi

doi:10.1109/ted.2003.822877

Cited by 79 publications

(46 citation statements)

References 13 publications

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“…This can be seen from the range of the data at a given dose, as well as the relative standard deviation (RSD). Variations in quantities such as doping concentration, transistor width, STI topology (planarity), and STI stress resulting from the contributions of process steps such as liner oxidation, high density-plasma oxide deposition, thermal oxidation processes after STI formation, and corner rounding effects in the STI [2][3][4][5][6][7][12][13][14][15] may contribute to the device-to-device variability as the dose increases.…”

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

“…These results are consistent with previously published results [7], conducted on only one process variant (LVT). In [7,14] the results are attributed to the mechanical stress from adjacent STI edges, which may affect the doping concentration at the STI sidewall, as well as the amount of charge trapping.…”

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

“…In particular, it has been shown that in a symmetric layout, the stresses from adjacent STI edges (STI space) are added to the original STI stress [7,14]. For narrow devices where the STI spacing is smaller, there is more compressive stress, which results in variations in both doping concentration and amount of charge trapping [17,18].…”

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

See 2 more Smart Citations

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Rezzak

Maillard

Schrimpf

et al. 2012

Microelectronics Reliability

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Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

Section: Comparison Of Off-state Leakage Current Variations For Diffementioning

confidence: 99%

See 1 more Smart Citation

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Rezzak

Maillard

Schrimpf

et al. 2012

Microelectronics Reliability

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“…The effects of the STI stress on device characteristics have been discussed in a few papers [1][2][3][4]. A few empirical models have been proposed in [5][6][7].…”

Section: The Simulation Of Sti Stressmentioning

confidence: 99%

Modeling of layout-dependent STI stress in 65nm Technology

Xue

Deng

et al. 2009

2009 IEEE 8th International Conference on ASIC

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In this work, we investigate the impact oflayout shapes on STI stress. Based on a stress simulator developed by us, we propose analytical models to correlate the STI stress and the layout parameters. Our model is validated by data collectedfrom a commercial 65nm process. The experimental results prove that the device characteristics predicted by our model closely match the measured data.Process simulators such as Taurus provide results with a high accuracy. However, they actually cannot consider the distribution of the STI stress of 2-D layout. Accordingly, we develop a new stress simulation tool [11], which is calibrated by Taurus simulation results on simple layout shapes. Using a finite element method, our stress simulator considers major stress sources, such as thermal mismatch, intrinsic stress, growth of materials and viscoelasticity, to perform highfidelity simulation of the STI stress. Fig. 2 shows a small Fi~. 1. Layout parameters related to STI stress stress distribution can be used to calibrate our stress simulator. With the stress simulator, the relation between the STI stress distribution and layout parameters can be studied in detail. Then we provide analytical models that could capture the impact of STI stress induced by arbitrary layout shapes. Finally we validate our model by applying it to analyze the subthreshold leakage current in 65nm technology.

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“…Systematic V th variation due to detailed difference in the environment has been attributed to stress, temperature, or ion implantation damage variation during fabrication process. 3,4 One of the key factors in device V th is junction overlap between gate and source/drain extension. 5 Therefore, the under-gate lateral dopant diffusion needs to be well controlled to avoid V th variation.…”

mentioning

confidence: 99%

Suppression of transient enhanced diffusion in sub-micron patterned silicon template by dislocation loops formation

2015

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We investigate the evolution of two dimensional transient enhanced diffusion (TED) of phosphorus in sub-micron scale patterned silicon template. Samples doped with low dose phosphorus with and without high dose silicon self-implantation, were annealed for various durations. Dopant diffusion is probed with plane-view scanning capacitance microscopy. The measurement revealed two phases of TED. Significant suppression in the second phase TED is observed for samples with high dose self-implantation. Transmission electron microscopy suggests the suppressed TED is related to the evolution of end of range defect formed around ion implantation sidewalls.

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Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics

Cited by 79 publications

References 13 publications

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

Modeling of layout-dependent STI stress in 65nm Technology

Suppression of transient enhanced diffusion in sub-micron patterned silicon template by dislocation loops formation

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