Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance

Freijedo, J.; Costas, Lucia; Semião, J.; Rodríguez-Andina, Juan J.; Moure, M.J.; Vargas, F.; Teixeira, I.C.; Teixeira, J.P.

doi:10.1166/jolpe.2010.1076

Cited by 19 publications

(6 citation statements)

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“…Examples of such threats include, among others, i) the growing susceptibility to α-particles and neutrons arriving from outer space or radioactive materials, yielding a nonnegligible degree of so called soft errors [1], ii) the noise affecting power supply lines which creates unexpected delays in critical paths [2], and iii) the Electromagnetic Interference (EMI), which can be inserted in the system over the air or through wires [3]. With increasing miniaturisation scales, a lesser amount of energy is required for an upset to reach the voltage threshold of the technology and generate a transient fault and, for the same amount of energy, those faults are shorter in duration [4].…”

Section: Introductionmentioning

confidence: 99%

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Espinosa

Andrés

Gil

2015

2015 11th European Dependable Computing Conference (EDCC)

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Abstract-Technology advances provide a myriad of advantages for VLSI systems, but also increase the sensitivity of the combinational logic to different fault profiles. Shorter and shorter faults which up to date had been filtered, named as fugacious faults, require new attention as they are considered a feasible sign of warning prior to potential failures. Despite their increasing impact on modern VLSI systems, such faults are not largely considered today by the safety industry. Their early detection is however critical to enable an early evaluation of potential risks for the system and the subsequent deployment of suitable failure avoidance mechanisms. For instance, the early detection of fugacious faults will provide the necessary means to extend the mission time of a system thanks to the temporal avoidance of aging effects. Because classical detection mechanisms are not suited to cope with such fugacious faults, this paper proposes a method specifically designed to detect and diagnose them. Reported experiments will show the feasibility and interest of the proposal.

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Section: Introductionmentioning

confidence: 99%

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Espinosa

Andrés

Gil

2015

2015 11th European Dependable Computing Conference (EDCC)

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“…Nevertheless, in the field of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs), sub-optimal approaches such as imposing guard-bands are still utilized to accommodate the Process, power supply Voltage, and Temperature (PVT) variations, and the maximum allowable clock frequencies reported by vendor synthesis, placement and routing tools are significantly lower than the ones that the device can really deliver [9]. Although there is ongoing research on the performance reliability and improvement of reconfigurable devices [10,11], none demonstrate the value and effectiveness of path-replica circuit for PVT.…”

Section: Introductionmentioning

confidence: 99%

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

Alnajjar

Mitsuyama

Hashimoto

et al. 2013

IEICE Electron. Express

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This paper studies performance and timing failure probability of time-shifted redundant circuits and path-/circuit-replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for the path-replica and circuit-replica, the false negative error probability of the circuit-replica is approximately two orders of magnitude less than that of the path-replica circuits. When attaining a false negative error of zero, the probability of error detection and reexecution in time-shifted redundant circuits is comparable to, or rather smaller than that of the path-replica circuits.

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“…Nevertheless, in the field of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs), sub-optimal approaches such as imposing guard-bands are still utilized to accommodate the Process, power supply Voltage, and Temperature (PVT) variations, and the maximum allowable clock frequencies reported by vendor synthesis, placement and routing tools are significantly lower than the ones that the device can really deliver [9]. Although there is ongoing research on the performance reliability and improvement of reconfigurable devices [10], [11], none demonstrate the value and effectiveness of replica circuit for PVT.…”

Section: Introductionmentioning

confidence: 99%

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

Alnajjar

Hashimoto

Onoye

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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This paper studies performance and timing failure probability of time-shifted redundant circuits and replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately two orders of magnitude less than that of the replica circuits. When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.

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Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance

Cited by 19 publications

References 0 publications

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

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