PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices

EDAC (Error Detection and Correction) techniques guarantee PVT variation safety by dynamically fixing timing error instead of providing static margins. However, previous EDAC works introduce additional area, power and performance penalty, thus the benefit from timing margin eliminating is limited. In this paper, we propose a novel EDAC Flip-Flop, EDSU, with ultra-low area overhead and nearly zero performance penalty. EDSU utilizes only two more transistors than conventional D-Flip Flop and can correct timing error simultaneously with detection. The ultra-lightweight property can obviously reduce area overhead and clock load, thus improve the variation tolerance ability and energy efficiency. EDSU is implemented in a commercial processor at SMIC 40 nm technology to evaluate its benefits. Simulation result shows EDSU inserted system gains 12.5% more performance at fixed voltage, 25% more variation tolerance and 10.5% energy saving at fixed throughput than state-of-art EDAC work.

Section: Introductionmentioning

confidence: 99%

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead

Hao

Xiang

Chen

et al. 2016

“…With the CMOS technology scaling down, process variation, voltage disturbance, temperature fluctuation and aging effects, known as PVTA variation, increase the unreliability of IC chips [1,2]. To address the variability of a chip, a typical way is setting excessive timing guard band in worst case.…”

Section: Introductionmentioning

confidence: 99%

TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor

Yong

Xiang

Meng

et al. 2016

Abstract:Recently, large efforts are made to achieve high throughput for aggressive voltage/frequency scaling in Error Detection and Correction system. In this paper, a zero-cycle penalty Timing-Borrowing and Clock Token (TBCT) based error correction method is proposed. A new error masking flip-flop is designed to enable time-borrowing and a clock token system is provided to pay back the borrowed time by locally shifting the clock phase of vulnerable flip-flops on the cascaded pipeline. The TBCT error correction method and error masking flip-flop are implemented into a 3-stage industrial Chinese microprocessor in a 40 nm CMOS process. Final experiment results show the proposed method achieves 1%-6% higher throughput than clock gating method and 9%-41% higher throughput than instruction replay.

Timing monitoring paths selection for wide voltage IC

Shan

Dai

Shi

et al. 2016

Wide voltage range circuit has got widespread attention where in-situ timing monitoring based adaptive voltage scaling (AVS) becomes necessary to reduce the design margin. However, the severe PVT variations across near-threshold to super-threshold cause too many critical paths to be monitored. Here activation oriented monitoring paths selection method is proposed to reduce the monitored paths for wide voltage IC. The minimum delay value of the longest activated path is found by dynamic timing analysis and set as the selection threshold. Those paths longer than this threshold by STA analysis are selected to be monitored. Applied on a 40 nm AVS Systemon-Chip, it reduces the monitoring paths to only 22% of all critical paths with remarkable power gains under 0.6 V-1.1 V.