EDSU: Error detection and sampling unified flip-flop with ultra-low overhead

Abstract

EDAC (Error Detection and Correction) techniques guarantee PVT variation safety by dynamically fixing timing error instead of providing static margins. However, previous EDAC works introduce additional area, power and performance penalty, thus the benefit from timing margin eliminating is limited. In this paper, we propose a novel EDAC Flip-Flop, EDSU, with ultra-low area overhead and nearly zero performance penalty. EDSU utilizes only two more transistors than conventional D-Flip Flop and can correct timing error simultaneously with detection. The ultra-lightweight property can obviously reduce area overhead and clock load, thus improve the variation tolerance ability and energy efficiency. EDSU is implemented in a commercial processor at SMIC 40 nm technology to evaluate its benefits. Simulation result shows EDSU inserted system gains 12.5% more performance at fixed voltage, 25% more variation tolerance and 10.5% energy saving at fixed throughput than state-of-art EDAC work.

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

“…A small change in the supply voltage will cause a large change in the delay. Furthermore, with the continuous process technology scaling, a PVT-induced delay increasingly exacerbates the timing conditions of synchronous circuits on both the clock signals and data paths [23]. Thus, the accuracy of logic circuits significantly reduces, resulting in the propagation of intolerable timing errors.…”

“…This method generates the error signals by capturing the abnormal transition of node signals caused by delay violations. This transistor-level detection method used in [10,12,[22][23][24] has a significant improvement in area and power, compared with the DSC method. However, most of these previous designs can only work at the super-threshold voltage (i.e., 0.8-1.2 V).…”

“…The EDAC designs have been researched for many NN accelerators [2,3,[5][6][7][8][9][10][11][12]19,20,27] and the circuits of microprocessors [13][14][15][16][17][18][21][22][23][24][25][26]. One prominent EDAC design is the Razor flip-flop (RFF) [13].…”

Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines

“…Two major design approaches have been proposed to address the issues with such large timing margins [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].…”

“…The second design approach involves detecting the real occurrence of a timing error and correcting it during runtime [11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26]. One of the most popular on-chip timingerror detection techniques involves double-sampling the data; in the first sampling, the main flip-flop/latch is utilized and in the second sampling, a shadow latch/flipflop driven by a delayed clock is utilized [11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].…”