Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

Abstract

This paper studies performance and timing failure probability of time-shifted redundant circuits and replica circuits. Measurement-based experiments using a fabricated test chip are performed. For an approximately similar false positive error probability for time-shifted redundant circuits and replica circuits, the false negative error probability of time-shifted redundant circuits is approximately two orders of magnitude less than that of the replica circuits. When attaining a false negative error of zero, time-shifted redundant circuits achieves one order of magnitude less in false positive error probability than that of the replica circuits.