Impact of high-k spacer on device performance of a junctionless transistor

Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

“…A high-k spacer element with HfO 2 (dielectric constant = 22) of length = 20 nm is used in this structure to bring improvement in the OFF-state characteristics [38]. The source-channel-drain region has a Gaussian doping profile characterized by a doping gradient of 2 nm/decade and with a peak doping concentration of 5 Â 10 19 cm À3 at the source and 2 Â 10 19 cm À3 at the drain.…”

Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

“…Uniform doping with zero doping gradient over the device represents junctionless transistor [5]. Junctionless transistors conducts with high φm that denotes the difference between the gate metal and channel material fully depletes the channel region [11][12][13][14][15]. To enhance better gate control over the channel and mobility, high-K spacer HfO2 is deposited.…”

A novel low leakage saddle junctionless FET with assistant gate

“…4,5 Some groups have also done a lot of research about the adjustments of gate spacer dielectric to decrease leakage current and improve analog characteristics. [6][7][8] Nevertheless, when the gate length is continuously reduced to extremely deep nanoscale (less than 15 nm, for example), the subthreshold properties of JL FETs will deteriorate again. [9][10][11] The shorter channel is less immune to the SCEs, and the distance between gate and source/drain contact is decreased, which triggers the prominent leakage current.…”

“…The geometry and material of gate in JL FETs have been modulated to obtain a better performance by changing the degree of energy band bending which is able to suppress the band‐to‐band tunneling . Some groups have also done a lot of research about the adjustments of gate spacer dielectric to decrease leakage current and improve analog characteristics . Nevertheless, when the gate length is continuously reduced to extremely deep nanoscale (less than 15 nm, for example), the subthreshold properties of JL FETs will deteriorate again .…”