Impact of Channel Hot Carrier Effect in Junction-and Doping-Free Devices and Circuits

Panchore, Meena; Singh, Jawar; Mohanty, Saraju P.

doi:10.1109/ted.2016.2619621

Cited by 28 publications

(7 citation statements)

References 15 publications

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“…In CP‐MOSFETs, source (n + /p + ) and drain (n + /p + ) regions are formed by depositing appropriate electrodes on the intrinsic silicon film that work on the concept of the work function ( ϕ mD ) difference of the connected materials, which is also known as the CP concept 26,27 . The fundamental specifications behind the CP concept are as follows: (a) the metal electrodes in the S/D region should have a work function such that ( ϕ mD < χ Si + E g /2) for N‐channel MOSFETs and ( ϕ mD > χ Si + E g /2) for P‐channel MOSFETs, and (b) the thickness of the silicon film should not be more than the Debye length L D 18,26 . The detail specification of device parameter is listed in Table 1.…”

Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

“…Apart from that, the dopingless structure has been investigated in previous study against channel hot carrier (CHC) degradation and heavy ion irradiation, and found less sensitive to these effects than the conventional structure. [16][17][18][19] In this manuscript, a catalytic metal gateimposed CP-MOSFET is proposed for improved sensitivity applications.…”

Section: Introductionmentioning

confidence: 99%

“…In this regard, charge plasma (CP) 14 based MOSFET has been explored by Sahu et al, 13,15 which reduces fabrication complexities, high thermal budget and it is also immune to process variation. Apart from that, the dopingless structure has been investigated in previous study against channel hot carrier (CHC) degradation and heavy ion irradiation, and found less sensitive to these effects than the conventional structure 16–19 . In this manuscript, a catalytic metal gate‐imposed CP‐MOSFET is proposed for improved sensitivity applications.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A highly sensitive MOSFET gas sensor based on charge plasma and catalytic metal gate

Dewangan,

Rajan,

Panchore

et al. 2023

Int J Numerical Modelling

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This manuscript presents, for the first time, a catalytic metal gate‐based charge plasma (CP) MOSFET with improved sensitivity for gas detection applications. In this design, CP refers to the source and drain boundaries being marked by depositing metal electrodes with appropriate work function over the intrinsic silicon film. To sense hydrogen and oxygen gases, palladium (Pd) and silver (Ag) metals are respectively deposited as gate electrodes on P‐CP‐MOSFET and N‐CP‐MOSFET. Further, sensitivity of CP‐MOSFET sensor is determined as if gas molecules are present and the results have been evaluated in comparison with the sensitivity of conventional gas sensor using bulk MOSFET in ATLAS TCAD device simulator. The effect of process variations on sensitivity has also been compared for both devices. The proposed device resolves fabrication complexity issues and offers better sensitivity.

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Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A highly sensitive MOSFET gas sensor based on charge plasma and catalytic metal gate

Dewangan,

Rajan,

Panchore

et al. 2023

Int J Numerical Modelling

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“…In DLJLFET structure, the silicon region doping is almost intrinsic; therefore, it is less susceptible to RDF and exhibits higher ON‐state current and smaller leakage current. Also, the electric filed in dopingless structure is quite less than conventional junctionless structure, thus making it more reliable from aging effect due to CHC 5–9 . However, the reliability of these scaled‐up devices has become extremely important and it depends on other stress factors also, for example, bias temperature instability (BTI).…”

Section: Introductionmentioning

confidence: 99%

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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In this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.

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“…The discrete and random nature of the impurity atom distribution, and their specific stochastic position in the device structure, is expected to greatly affect the performance of such devices [15,16]. Hence, effects associated with random dopant fluctuations (RDF) are anticipated to have greater impact for gate-lengths below 10 nm [17,18]. Therefore, understanding the stochastic statistical behavior of JNTs in the presence of random dopant atoms is of great interest.…”

Section: Introductionmentioning

confidence: 99%

Random dopant fluctuations and statistical variability in n-channel junctionless FETs

Akhavan

Umana‐Membreno²,

Gu³

et al. 2017

Nanotechnology

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The influence of random dopant fluctuations on the statistical variability of the electrical characteristics of n-channel silicon junctionless nanowire transistor (JNT) has been studied using three dimensional quantum simulations based on the non-equilibrium Green's function (NEGF) formalism. Average randomly distributed body doping densities of 2 × 10, 6 × 10 and 1 × 10 cm have been considered employing an atomistic model for JNTs with gate lengths of 5, 10 and 15 nm. We demonstrate that by properly adjusting the doping density in the JNT, a near ideal statistical variability and electrical performance can be achieved, which can pave the way for the continuation of scaling in silicon CMOS technology.

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Impact of Channel Hot Carrier Effect in Junction-and Doping-Free Devices and Circuits

Cited by 28 publications

References 15 publications

A highly sensitive MOSFET gas sensor based on charge plasma and catalytic metal gate

A highly sensitive MOSFET gas sensor based on charge plasma and catalytic metal gate

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Random dopant fluctuations and statistical variability in n-channel junctionless FETs

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