2009 Proceedings of ESSCIRC 2009
DOI: 10.1109/esscirc.2009.5325994
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Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

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Cited by 24 publications
(17 citation statements)
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“…In this paper, tested devices are FDSOI nMOS transistors with body contacts. This technology is developed at CEA/LETI-Minatec and is optimized for the 20 nm node [23]. The SOI active layer is 8-nm thick and the gate length varies from 10 m down to 30 nm.…”
Section: Fully Depleted Soi Technologymentioning
confidence: 99%
“…In this paper, tested devices are FDSOI nMOS transistors with body contacts. This technology is developed at CEA/LETI-Minatec and is optimized for the 20 nm node [23]. The SOI active layer is 8-nm thick and the gate length varies from 10 m down to 30 nm.…”
Section: Fully Depleted Soi Technologymentioning
confidence: 99%
“…The Fully Depleted (FD) SOI MOSFET with Ultra Thin Buried Oxide (UTBOX) is considered as one of the best candidates for the sub 32nm technology nodes due to the better short channel effect maintaining the well known planar structure (1).…”
Section: Introductionmentioning
confidence: 99%
“…This is the reason why, this method has been extensively used by different groups worldwide [17][18][19][20][21]. This code has been calibrated by comparing to experimental data obtained from [22] and with MS deterministic simulators as shown in [23]. In the same way it has demonstrated its capabilities studying different advanced bulk and SOI planar nanodevices [24][25][26][27].…”
Section: Simulation Methodologymentioning
confidence: 99%