Image filter evolution on the Xilinx Zynq Platform

Dobai, Roland; Sekanina, Lukáš

doi:10.1109/ahs.2013.6604241

Cited by 21 publications

(14 citation statements)

References 17 publications

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“…Glette et al [2009] use the shift functionality of lookup tables (LUTs) in order to reduce the area requirements. The chromosome is not stored in the configuration register but shifted immediately into the LUT.…”

Section: Fpga-based Ehw Systemsmentioning

confidence: 99%

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Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Dobai

Sekanina

2015

ACM Trans. Reconfigurable Technol. Syst.

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Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Virtual reconfiguration is based on the change of functionality by hardware components implemented on top of FPGA resources. Native reconfiguration changes the FPGA resources directly by means provided by the FPGA manufacturer. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all-programmable system-on-chip. The proposed architecture offers high flexibility in comparison with other evolvable hardware systems by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast evaluation of candidate solutions. The proposed architecture is evaluated by evolutionary design of switching image filters and edge detectors. The experimental results demonstrate advantages over the previous approaches considering the time required for evolution, area overhead, and flexibility. ACM Reference Format:Roland Dobai and Lukas Sekanina. 2015. Low-level flexible architecture with hybrid reconfiguration for evolvable hardware.

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Section: Fpga-based Ehw Systemsmentioning

confidence: 99%

“…Other reconfiguration approaches have also been published [Glette et al 2009;Bartolini et al 2013]. Glette et al [2009] use the shift functionality of lookup tables (LUTs) in order to reduce the area requirements.…”

Section: Fpga-based Ehw Systemsmentioning

confidence: 99%

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Dobai

Sekanina

2015

ACM Trans. Reconfigurable Technol. Syst.

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“…In fact, the memory bandwidth often poses the bottleneck in HW/SW-codesigns and therefore limits the overall performance: While it is possible to achieve a very high throughput in an FPGA, the memory interface is in many cases not able to provide input and store output data fast enough [1,2]. Therefore, many research papers are only presenting the throughput inside the FPGA while disregarding the memory bandwidth [3,4]. For this reason, this work presents an analysis of the memory architecture of FPGA-SoCs.…”

Section: Introductionmentioning

confidence: 99%

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

Göbel

Elhossini

Ching³

et al. 2017

Lecture Notes in Computer Science

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Abstract. In recent years, so called FPGA-SoCs have been introduced by Intel (formerly Altera) and Xilinx. These devices combine multi-core processors with programmable logic. This paper analyzes the various memory and communication interconnects found in actual devices, particularly the Zynq-7020 and Zynq-7045 from Xilinx and the Cyclone V SE SoC from Intel. Issues such as different access patterns, cache coherence and full-duplex communication are analyzed, for both generic accesses as well as for a real workload from the field of video coding. Furthermore, the paper shows that by carefully choosing the memory interconnect networks as well as the software interface, high-speed memory access can be achieved for various scenarios.

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“…In the end of year 2015 over 30 SoC-based papers were available in the most popular databases. They cover different topics: -image filtering [16], -feature extraction [28,60], -optical flow computation [42], -road sign recognition [54], -driver awareness monitoring system [56], -face detection [23,77], -stereovison system [10], -object detection and tracking [49], -advanced driver assistance systems [59].…”

Section: Introductionmentioning

confidence: 99%

Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC

Kryjak

Komorkiewicz

Gorgon

2016

J Real-Time Image Proc

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The article demonstrates the usefulness of heterogeneous System on Chip (SoC) devices in smart cameras used in intelligent transportation systems (ITS). In a compact, energy efficient system the following exemplary algorithms were implemented: vehicle queue length estimation, vehicle detection, vehicle counting and speed estimation (using multiple virtual detection lines), as well as vehicle type (local binary features and SVM classifier) and colour (k-means classifier and YCbCr colourspace analysis) recognition. The solution exploits the hardwaresoftware architecture, i.e. the combination of reconfigurable resources and the efficient ARM processor. Most of the modules were implemented in hardware, using Verilog HDL, taking full advantage of the possible parallelization and pipeline, which allowed to obtain real-time image processing. The ARM processor is responsible for executing some parts of the algorithm, i.e. high-level image processing and analysis, as well as for communication with the external systems (e.g. traffic lights controllers). The demonstrated results indicate that modern SoC systems are a very interesting platform for advanced ITS systems and other advanced embedded image processing, analysis and recognition applications.Keywords Intelligent Transportation Systems Á Hardware-software image processing (Zynq SoC) Á Vehicle queue length estimation Á Vehicle detection Á Vehicle type and colour recognition

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Image filter evolution on the Xilinx Zynq Platform

Cited by 21 publications

References 17 publications

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

A Quantitative Analysis of the Memory Architecture of FPGA-SoCs

Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC

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