IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters

Tilden, Steven J.; Max, S.; Blair, Jerry; Alegria, F.; Balestrieri, E.; Björsell, Niclas; Calvin, J.; Dallet, Dominique; Daponte, P.; Vito, Luca De; Гончаренко, А. М.; Greer, Deirdre; Liggiero, Richard; Linnenbrink, Tom E.; Rapuano, Sergio; Xu, Fei

doi:10.1109/ieeestd.2011.5692956

Cited by 56 publications

(54 citation statements)

References 26 publications

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“…The test methods mentioned above are described in detail in the IEEE standard [1]. Furthermore, this document defines rather strict conditions for the signal parameters which have to be fulfilled to ensure accurate results.…”

Section: Introductionmentioning

confidence: 99%

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

2015

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Analog-to-digital converters and the need to test these devices appeared simultaneously. Thus, ADC circuit realizations and test methods evolved also simultaneously. In the last decades several techniques have been elaborated and spread worldwide. These are available in IEEE standards and in the literature as well. However, standard methods do not support the recognition of incorrect measurement settings. Accurate test results require careful choice of settings and calculated quality parameters of the ADC under test are very sensitive to imperfections of the measurement setup. In addition, the requirements are different for each test technique and the restrictions can even be contradicting (e.g. overdrive is recommended for histogram test and contraindicated for FFT test). This paper presents solutions to perform the commonly used methods reliably and some advanced methods to increase the performance of ADC quality parameter estimation. Implementations of the proposed algorithms are presented as well, with URL for download.

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Section: Introductionmentioning

confidence: 99%

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

2015

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“…where h spur À h 1 can be obtained by measuring the height difference in decibels between SJ-induced spur and the fundamental bin in ADC spectrum; f in can be estimated in frequency domain if the collected data is coherent [2], and this parameter is also needed in the following RJ estimation. Then the RMS value of SJ is B= ffiffi ffi 2 p .…”

Section: Sj Estimationmentioning

confidence: 99%

“…where T s represents ideal sampling period; tj k represents the total clock jitter at sampling instant kT s ; V h ðkT s Þ is harmonic distortion component caused by the nonlinearity of ADC; V n ðkT s Þ is ADC input-referred noise caused by ADC thermal noise and quantization noise [2], and it follows normal distribution: V n ðkT s Þ $ Nð0; 2 n Þ. M is the data record length. In this letter, the total clock jitter tj k consists of two components: SJ and RJ, as shown in (6).…”

Section: Clock Jitter Measurement In Adc Testmentioning

confidence: 99%

“…Clock jitter, defined as a random variation in the sampling instant, is an important test metric in high-speed analog-to-digital converter (ADC) test or other sampling circuits test [1,2,3]. This parameter is of special importance as the signal frequency and data rate increasingly get higher.…”

Section: Introductionmentioning

confidence: 99%

“…This parameter is of special importance as the signal frequency and data rate increasingly get higher. In some applications, clock jitter, especially sinusoidal jitter (SJ) and random jitter (RJ), has become the bottleneck of many systems performance [2].…”

Section: Introductionmentioning

confidence: 99%

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Extracting random jitter and sinusoidal jitter in ADC output with a single frequency test

Liu

Chen

2015

IEICE Electron. Express

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An accurate and low-cost technique is proposed for sinusoidal jitter and random jitter estimation in high-speed ADC test. Exploiting the fact that clock jitter is modulated by the slope of input signal, the proposed method can simultaneously extract both information for sinusoidal jitter and random jitter with a single high frequency test. The proposed method is computationally efficient since only one FFT, one IFFT and few simple arithmetic operations are involved. Compared with existing dual-frequency tests and single-frequency tests, both hardware overhead and data acquisition time are saved significantly. Theoretical analysis and simulation results validate the computational efficiency and test accuracy.

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A 12‐bit SC³ partially segmented current steering DAC with improved SFDR and bandwidth

Kumar

Gupta

Bhadauria

2022

Circuit Theory & Apps

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A 12‐bit self cascode capacitor compensated (SC3) partial segmented current steering digital to analog converter (DAC) is proposed and implemented in standard 180‐nm CMOS technology. The effect of the output capacitance at a higher frequency of operation is analyzed. Based on the analysis, a self cascode transistor is connected on the top of the differential switch with an “always‐on” biasing without compromising the voltage headroom. Besides, a compensation capacitor is also used at the output to improve spur free dynamic range (SFDR), which is obtained as 108 dB when sampled at 800 MS/s. The proposed architecture also offers high output impedance by more than 10 times compared with the cascode device. The proposed design also enhances the bandwidth of the circuit and is obtained to be 4 GHz with a power supply rejection ratio (PSRR) of 43 dB. It also has a total harmonic distortion (THD) of <3% up to input power of −4 dB and is also insensitive to process variations with a sensitivity of <0.5%.

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IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters

Cited by 56 publications

References 26 publications

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

Extracting random jitter and sinusoidal jitter in ADC output with a single frequency test

A 12‐bit SC³ partially segmented current steering DAC with improved SFDR and bandwidth

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IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters

Cited by 56 publications

References 26 publications

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

Full information ADC test procedures using sinusoidal excitation, implemented in MATLAB and LabVIEW

Extracting random jitter and sinusoidal jitter in ADC output with a single frequency test

A 12‐bit SC3 partially segmented current steering DAC with improved SFDR and bandwidth

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Product

Resources

About

A 12‐bit SC³ partially segmented current steering DAC with improved SFDR and bandwidth