IEEE-1149.x standards: achievements vs. expectations

Ungar, Louis Y.; Bleeker, Harry; McDermid, J.; Hulvershorn, H.

doi:10.1109/autest.2001.948964

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…Several IEEE 1149.x standards and proposed standards were developed by the test community since the mid-1980s, when the Joint Test Action Group (JTAG) initiated the development of the test technology that became known as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. The approval of IEEE 1149.1 in 1990 marked the beginning of a series of IEEE 1149.x test standards that include successful and unsuccessful attempts to provide industry-accepted production test technologies [6]. The IEEE 1149.5 Standard for Module Test and Maintenance Bus (MTM-Bus) Protocol [7], and the IEEE 1149.4 Standard for a Mixed-Signal Test Bus [8], are two examples of proposals that met little or no industry acceptance, in spite of having become recognized IEEE standards.…”

Section: Ieee 1149x Standards and Test Command Setmentioning

confidence: 99%

An IEEE 1149.x Embedded Test Coprocessor

Gebremeskel¹,

Ferreira²

2014

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This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations; 2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

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Section: Ieee 1149x Standards and Test Command Setmentioning

confidence: 99%

An IEEE 1149.x Embedded Test Coprocessor

Gebremeskel¹,

Ferreira²

2014

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“…Although a daisy chain of IEEE-1149.1 test access ports (TAPs) could be used instead, the failure of any board in the chain would complicate diagnosis. 9 Although not all boundary-scanned ICs have IC BIST, ICs with internal BIST can usually get their information directly to the 1149.1 TAP. In Figure 3, boards are also equipped with board-level BIST.…”

Section: Cost Areamentioning

confidence: 99%

Economics of built-in self-test

Ungar

Ambler

2001

IEEE Des. Test. Comput.

Self Cite

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costs and few benefits. The truth lies somewhere in between these two extremes. The ideal solution is a sound economic model that lets designers-who have products with various production volumes, design complexities, specifications, support requirements, and customer stress levels-better determine what type of BIST, if any, is best for their applications.IC manufacturers evaluate the benefits and costs of wafer-, intellectual-property-, system-ona-chip-, and IC-level BISTs based on profit margin impact. Board manufacturers typically focus on the economics of boundary scan and boardlevel BIST implementations, although they should also consider the benefits derived from IC-level BIST. Board-level BIST, a relatively new phenomenon, 1 integrates IC-level, boundary scan, and board-level logic BIST for both circuit card vendors and system integrators. System manufacturers consider system-, board-, and IClevel BIST in determining the economics of the Economics of Built-in Self-Test International Test Conference 70 Using built-in self-test at the right level offers users significant cost savings, but determining which level, if any, is best for BIST can be complex. A detailed economic analysis can unravel heterogeneous costs and benefits so that designers and managers can make the right decision. Design and test Design, design for testability (DFT) and test time, budgeting considerations, marketing, quality and reliability, target throughput, training, packaging technology, circuit layout, silicon, pin out, CAD tools, designers' skills, performance degradation, computing equipment, and capital investment DFT and ATE Purchasing, depreciation and maintenance, operator and programming salaries, other labor rates, setup time, test program length, pin memory, program fault coverage, program preparation time, test and diagnosis time, test fixtures, manufacturing yield, production volume, and number of board types Field service Repair depot, logistics support, field repair, downtime, repeat visits, and design for maintainability

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Boundary Scan and Core-Based Testing

Lee

2006

VLSI Test Principles and Architectures

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IEEE-1149.x standards: achievements vs. expectations

Cited by 12 publications

References 7 publications

An IEEE 1149.x Embedded Test Coprocessor

An IEEE 1149.x Embedded Test Coprocessor

Economics of built-in self-test

Boundary Scan and Core-Based Testing

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