Boundary Scan and Core-Based Testing

Lee, Kuen Jong

doi:10.1016/b978-012370597-6/50014-7

VLSI Test Principles and Architectures 2006

DOI: 10.1016/b978-012370597-6/50014-7

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Boundary Scan and Core-Based Testing

Kuen Jong Lee

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2010

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“…[2]. The test data is shifted into the boundary-scan daisy chain from TDI pin of Chip 1 when the TAP (Test Access Port) controllers of both chips are in the Shift-DR state.…”

mentioning

confidence: 99%

Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

Zhao

Han

et al. 2010

AMR

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An approach for detecting open and short faults on the interconnect wires of a multi-FPGA system will be presented in this paper. In a multi-FPGA system with N interconnects, this approach can detect whether and where an open fault occurs by executing the IEEE 1149.1 JTAG EXTEST instruction once. To detect a single short fault, on the other hand, needs execution of times where . If multiple short connections exist, this approach will only detect the first short fault. The test time is thus greatly reduced for finding a single short fault per chip. Simulation results demonstrate that this approach can be easily implemented and determines accurate locations of the open/short faults.

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“…[2]. The test data is shifted into the boundary-scan daisy chain from TDI pin of Chip 1 when the TAP (Test Access Port) controllers of both chips are in the Shift-DR state.…”

mentioning

confidence: 99%

Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

Zhao

Han

et al. 2010

AMR

View full text Add to dashboard Cite

show abstract

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Boundary Scan and Core-Based Testing

Cited by 1 publication

References 51 publications

Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

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