Economics of built-in self-test

Ungar, Louis Y.; Ambler, T.

doi:10.1109/54.953274

Cited by 25 publications

(5 citation statements)

References 9 publications

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“…This inputs can share a single signal in test mode without sacrificing fault coverage, hence the test storage is reduced. To expand the patterns to their original format during test application, a kind of decode circuit is shown as fig 3.…”

Section: Fig 2 Stumps Bist Architecturementioning

confidence: 99%

An Efficient Two-Dimension BIST Compression Approach

Wang

Zheng

et al. 2015

AMM

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In this paper a two-dimension BIST compression scheme is presented; the proposed scheme is utilized in order to drive down the number of deterministic vectors to achieve complete fault coverage in BIST applications. By introducing shifting compression and input reduction, vertical and horizontal compression are realized respectively to achieve two-dimension BIST compression. Experimental results show that the BIST shifting compression based on input reduction can achieve great compression rate as much as 99%. Comparisons with previously competitive presented schemes indicate that the proposed scheme provide an efficient BIST compression approach with lower storage overhead.

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Section: Fig 2 Stumps Bist Architecturementioning

confidence: 99%

An Efficient Two-Dimension BIST Compression Approach

Wang

Zheng

et al. 2015

AMM

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“…With the appropriate access features, the BIST can be reused at subsequent levels of product integration such as boards and systems. An economics framework of BIST and boundary scan has been carried out by various researchers (Miranda, 1997; Lu and Wu, 2000; Wei et al , 1997; Lin et al , 1998; Ungar and Ambler, 2001).…”

Section: Testingmentioning

confidence: 99%

“…Successful design and test involves many factors such as time to market, quality perception, market place, product life time, and so on. Economic analyses can be quit helpful for designers in decision making (Wei et al , 1997; Lin et al , 1998; Ungar and Ambler, 2001).…”

Section: Testingmentioning

confidence: 99%

VLSI interconnects and their testing: prospects and challenges ahead

Sharma¹,

Kaushik

Sharma

2011

Journal of Engineering, Design and Technology

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PurposeThe purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.Design/methodology/approachIn the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.FindingsThe effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.Originality/valueThis paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

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“…A built-in self-test (BIST) is one of the most challenging techniques for integrated circuits. BISTs can help save costs on the initial design [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

A BIST Scheme for Dynamic Comparators

Tang

Tachibana

2022

Electronics

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in dynamic comparators. In this scheme, a feedback loop is designed using the characteristics of the comparator; monitoring the voltage in the feedback loop can determine the presence of a circuit fault. The proposed BIST scheme and the circuit under testing are realized at the transistor level. The proposed BIST scheme was simulated using HSPICE. The simulated fault coverage is approximately 87.8% with 90 test circuits. To further verify the effectiveness of the proposed BIST scheme, six faults were injected into the real circuit. The test results were consistent with the simulation results.

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Economics of built-in self-test

Cited by 25 publications

References 9 publications

An Efficient Two-Dimension BIST Compression Approach

An Efficient Two-Dimension BIST Compression Approach

VLSI interconnects and their testing: prospects and challenges ahead

A BIST Scheme for Dynamic Comparators

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