(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

Abstract

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.

Asynchronously Pulsed Plasma for High Aspect Ratio Nanoscale Si Trench Etch Process

“…The feature size of electronic devices is continuously decreasing, and advanced patterning technology such as SADP (self-aligned double patterning), SAQP (self-aligned quadruple patterning), etc. is being adopted even for EUV (extreme ultraviolet) lithography technology to realize devices having a CD (critical dimension) of less than 10 nm. − In addition to the complexities involved in the extremely small-scale patterning process, the geometrical change of device structure from 2D to 3D makes the patterning process extremely difficult. − For this reason, there are many issues that occur during the plasma etching process, and one of the important issues that arises with increasing aspect ratio of the device feature is the ARDE (aspect ratio dependent etching) effect, which shows different etch depth depending on the pattern width, due to the ion/neutral shadowing, charging of the mask, Knudsen transport of neutrals, etc. − …”

Dry etching of ternary metal carbide TiAlC via surface modification using floating wire-assisted vapor plasma

“…In a fin-type or nanosheet field effect transistor (FET) of a logic semiconductor device, it has been proposed to use metal gate materials, for examples, metal carbides (TiC, TiAlC) and metal nitrides (TiN, TaN, AlN, TiAlN) 1 – 5 . Ternary metal compound such as TiAlC belongs to high-melting point, high-hardness, and high-wear resistance materials 1 , 6 , 7 .…”

“…Ternary metal compound such as TiAlC belongs to high-melting point, high-hardness, and high-wear resistance materials 1 , 6 , 7 . Conventionally, the TiAlC film and TiC film in semiconductor devices are etched by wet etching using H 2 O 2 mixtures 5 , 8 – 10 . However, a poor metal removability in wet etching requires a prolonged etching time to fully remove the target metals, and in the worst case, the metal gate can be damaged 5 .…”

“…Conventionally, the TiAlC film and TiC film in semiconductor devices are etched by wet etching using H 2 O 2 mixtures 5 , 8 – 10 . However, a poor metal removability in wet etching requires a prolonged etching time to fully remove the target metals, and in the worst case, the metal gate can be damaged 5 . In order to fabricate the next generation FETs in semiconductor industries, it is strongly demanded to develop an etching method that enables to control the selective and isotropic removal of metal carbides (TiAlC, TiC, and AlC) at an atomic layer level 5 , 9 , 10 .…”

“…However, a poor metal removability in wet etching requires a prolonged etching time to fully remove the target metals, and in the worst case, the metal gate can be damaged 5 . In order to fabricate the next generation FETs in semiconductor industries, it is strongly demanded to develop an etching method that enables to control the selective and isotropic removal of metal carbides (TiAlC, TiC, and AlC) at an atomic layer level 5,9,10 . No dry etching (plasma etching) of ternary material TiAlC with atomic level control has been developed yet.Atmospheric pressure plasma (APP) and medium-pressure plasma techniques with a large difference in chemical kinetics compared to low-pressure plasma are able to miniaturize equipment size, fabrication cost, and energy consumption [11][12][13][14][15][16][17] .…”