<i>Digital Signal Processor</i>: Architecture and Performance

Boddie, J.; Daryanani, G.; Eldumiati, I. I.; Gadenz, R.; Thompson, John; Walters, S.

doi:10.1002/j.1538-7305.1981.tb00278.x

Cited by 34 publications

(6 citation statements)

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“…1 The order in which these operations are executed, as well as the way in which the threshold detector is implemented, are described below.…”

Section: The Dsp Algorithmmentioning

confidence: 99%

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Digital Signal Processor: Tone Detection for CCITT No. 5 Transceiver

Gadenz¹

1981

Bell System Technical Journal

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“…1 The order in which these operations are executed, as well as the way in which the threshold detector is implemented, are described below.…”

Section: The Dsp Algorithmmentioning

confidence: 99%

“…The application of a recently developed LSI digital signal processor, the DSP, 1 to tone detection in a proposed digital CCITT NO. 5 signaling unit is described.…”

Section: Introductionmentioning

confidence: 99%

Digital Signal Processor: Tone Detection for CCITT No. 5 Transceiver

Gadenz¹

1981

Bell System Technical Journal

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“…The multiplier units are capable of performing operations on operands of various data types such as calculating running sum of products. As multiplication is a crucial arithmetic operation in processors [5] and digital computer systems, multipliers are the core building block for many algorithms in a wide variety of computing applications. Although multipliers are main arithmetic components used for processing scientific data, the excessive power consumption and delay attracts attention from the research community.…”

Section: Introductionmentioning

confidence: 99%

Design of modified booth based multiplier with carry pre-computation

Cvs¹,

Sundaresan²,

Venkateswaran³

et al. 2019

IJEECS

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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

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“…The chip photograph is shown in The addess generation unit also contains three address registers (AR1 through AR3) each associated with three parts of data memory and two second ad- (3) dress registers (SAR2 and SAR3) for two data RAMs. The address registers generate the address in the form of eq.…”

Section: Developed Signal Processormentioning

confidence: 99%

“…Furthermore, the advent of single-chip digital signal processors (1)(2)(3) added economic viability to digital irs7lementation as deronstrated in successful realization of voiceband equipment like dualtone multifrequency receivers and low-speed modems.…”

Section: Introductionmentioning

confidence: 99%

An LSI digital signal processor

Yano

Inoue²,

Senba³

ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing

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This paper describes a recently developed single-chip digital signal processor designed to satisfy the requirements of a wide range of telecommunication applications. The device is fabricated with N-channel MOS technology and contains 65,000 transistors within a 7.9 by 7.44 mm area. It has many features for efficient pipelined operations and achieves a high degree of throughput. The processor also has large data memories: 512 words of ROM and 256 words of RAM. The I/O unit includes an on-chip DMA controller which allows the processor to be readily Interfaced with other devices. Multiprocessor systems are constructed with no external logic.

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Digital Signal Processor: Architecture and Performance

Cited by 34 publications

References 0 publications

Digital Signal Processor: Tone Detection for CCITT No. 5 Transceiver

Digital Signal Processor: Tone Detection for CCITT No. 5 Transceiver

Design of modified booth based multiplier with carry pre-computation

An LSI digital signal processor

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