Design of modified booth based multiplier with carry pre-computation

Cvs, Chaitanya; Sundaresan, C; Venkateswaran, P. R.; Prasad, K. J. Rajendra

doi:10.11591/ijeecs.v13.i3.pp1048-1055

Cited by 3 publications

(2 citation statements)

References 5 publications

(5 reference statements)

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“…The Booth algorithm (Tariq et al, 2016)- (Chaitanya et al, 2019) performs the operation by generates a 2n-bit product and make both positive and negative 2's complement n-bit operands uniformly. As a basis operation of this algorithm, consider a multiplication operation which multiplier is positive and has a single block of 1s.…”

Section: Booth Multipliermentioning

confidence: 99%

Booth Algorithm with Implementation of UART Module using FPGA

Mahamad,

Sidek,

Saon

et al. 2020

IJIE

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FPGA gives high level of flexibility to the user to rapidly construct and test any hardware. It has a lot of gates which are used depending upon the hardware to be implemented. These project aims at designing Booth multiplier using VHDL for signed bit multiplication in FPGA for high speed operations, developed and implemented of UART module required to enable two-way communication between the DE-2 board and computer. It is also designed GUI interface using MATLAB for sending data and enable the output of the process result to be displayed. The Booth multiplier was implemented using the algorithm in both signed and unsigned number and the input and output of the multiplication was successfully achieved and confirmed through simulation. The GUI was implemented and tested, which UART module also performed well for transmitting and receiving of 8-bit width data. In general, the objective of this project was successfully achieved, which, the result of the component part were able to be tested.

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Section: Booth Multipliermentioning

confidence: 99%

Booth Algorithm with Implementation of UART Module using FPGA

Mahamad,

Sidek,

Saon

et al. 2020

IJIE

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“…To represent 32-bit and 64-bit floating point numbers IEEE 754 standard format is used [26]. Booth-based multiplication is used to pre-calculate the carry and the presented design improved the speed and dissipated less power with respect to the existing multipliers [27]. A fast-floating point unit is designed and implemented for FPGAs [28].…”

Section: Introductionmentioning

confidence: 99%

Comparative study of single precision floating point division using different computational algorithms

Singh¹,

Parihar²

2023

IJRES

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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>

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Reversible logic in pipelined low power vedic multiplier

Eshack¹,

Krishnakumar²

2019

IJEECS

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<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

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Design of modified booth based multiplier with carry pre-computation

Cited by 3 publications

References 5 publications

Booth Algorithm with Implementation of UART Module using FPGA

Booth Algorithm with Implementation of UART Module using FPGA

Comparative study of single precision floating point division using different computational algorithms

Reversible logic in pipelined low power vedic multiplier

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