Hyper node torus: A new interconnection network for high speed packet processors

Khosravi, Atefeh; Khorsandi, Siavash; Akbari, Mohammad Kazem

doi:10.1109/cnds.2011.5764553

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…However, the dimension routing algorithm is not adaptive and it does not exploit all the paths within the network, hence putting a limit on the performance for large-scale parallel systems. Hyper nodes torus is an architecture that extends torus interconnection by replacing each node in the torus with a ring [29]. A distributed environment is laid down as each node can be either a memory or a processor.…”

Section: Related Workmentioning

confidence: 99%

HyperZ: Hyper Z-Tree Topology

Adda¹

2023

Preprint

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Multi-level direct networks fueled by the evolving technology of active optical cables and increasing pin-bandwidth achieve reduced diameters and cost, with high-radix switches. These networks, like Dragonfly, are becoming the preferred aspirants for extreme high-performance parallel machines such as exa-scale computing. In this paper, we introduce a Hyper Z-Tree topology, which deploys the Z-Tree, a variant of fat-tree, as a computing node of a Generalized Hypercube (GHC) configuration. The resulting configuration provides higher bisection bandwidth, lower latency for some applications and higher throughput. Furthermore, the levels of the fat tree offer several path diversities across the GHC dimensions, hence conceding a more fault tolerant architecture. To profit from these path diversities, we propose two adaptive routing algorithms, which are extensions to the routing algorithm suggested in HyperX topology. These two algorithms exhibit better latencies and throughput than the HyperX.

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Section: Related Workmentioning

confidence: 99%

HyperZ: Hyper Z-Tree Topology

Adda¹

2023

Preprint

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“…In[13], the evaluation is strictly based on uniform versus Hotspot traffic for two specific NoC topologies, while in[14], the evaluation is restricted in varying PIR. Similar works have been focused exclusively on specific NoC topologies as well[15] [16]. In[17], NoC behavior is ex-amined under three communications processes namely TCP, VBR and CBR for paper proposes an evaluation of routing algorithm impact on traffic engineering and performance specified via QoS metrics, such as average delays and throughputs in 2D NoCs, under different values of critical importance parameters, as spatial and time distribution traffic profiles, or more realistic Hotspot traffic profiles, while varying buffer size, PIR, packet size and network size, either individually or as a set.…”

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confidence: 99%

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Lallas¹

2021

ENG

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Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

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Performance Evaluation of Multi-Core Multi-Cluster Architecture (MCMCA)

Hamid

Walters

Wills

2015

Advances in Systems Analysis, Software Engineering, and High Performance Computing

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A multi-core cluster is a cluster composed of numbers of nodes where each node has a number of processors, each with more than one core within each single chip. Cluster nodes are connected via an interconnection network. Multi-cored processors are able to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. A general problem in the network arises from the fact that multiple messages can be in transit at the same time on the same network links. This chapter considers the communication latencies of a multi core multi cluster architecture, investigated using simulation experiments and measurements under various working conditions.

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Hyper node torus: A new interconnection network for high speed packet processors

Cited by 3 publications

References 5 publications

HyperZ: Hyper Z-Tree Topology

HyperZ: Hyper Z-Tree Topology

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Performance Evaluation of Multi-Core Multi-Cluster Architecture (MCMCA)

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