An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Abstract

Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

“…Although theoretically asynchronous NICs can use any routing algorithm, limited by the complexity of router implementation, asynchronous NICs mostly use deterministic routing algorithms [23], and only a smaller number of asynchronous on-chip networks started using adaptive routing algorithms to increase network reliability. There are two main types of deterministic routing algorithms used in asynchronous on-chip networks: source routing and XY routing [24]. Source routing requires the originating node of the message to pre-determine the communication path and store the path in the header microchip of the message, while XY routing only needs to store the address of the destination node of the message in the header microchip, and the router will automatically specify the address according to the address path.…”