Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node

Choi, Soo-Han; Park, Ji-Soong; Park, Chul‐Hong; Chung, Won-Young; Kim, In-Sung; Kim, Dong-Hyun; Kim, Yoo-Hyon; Yoo, Moon-Hyun; Kong, Jeong-Taek

doi:10.1117/12.485397

Cited by 5 publications

(4 citation statements)

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“…In our previous study [9], the multi-step correction modifies the target CD after photo process to compensate the etch loading effect. The multi-step correction of this paper modifies the target CD after photo process to accomplish sufficient process margins of the dense area.…”

Section: Results Of Litho-friendly Layout Design and Model-based Opcmentioning

confidence: 99%

Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

et al. 2004

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As the lithography process approaches to the low k1 regime, the layout designers are forced to design the lithofriendly layout, which considers the process margin and mask error enhancement factor (MEEF). In addition, the lithography engineers are also impelled to optimize the optical proximity correction (OPC) rules at the full-chip level to eliminate the failures of the printed image on the wafer. Therefore, we have newly developed the simulation-based critical area extraction (CAE) and litho-friendly layout (LFL) design methodology based on the layout editor environment to design the litho-friendly layout and optimize the OPC rules. In this methodology, the critical areas of the full-chip level post-OPC layout, which have the lower process margin and larger critical dimension (CD) variation, are automatically extracted by evaluating the focus-exposure window, normalized image log-slope (NILS) and edge placement error (EPE). The extracted critical areas are sorted according to their causes of failures (i.e., notching, bridging, line-end shortening and larger CD variation, etc.). In order to maximize the process margin and minimize the MEEF at the full-chip level, layout designers and lithography engineers modify the original layout and optimize the OPC rules of the sorted critical areas based on the lithography simulator. The simulator uses the mask decomposition and selective simulation method to reduce the simulation time at the full-chip level. For the convenient CAE, process margin evaluation and layout optimization, the CAE function and lithography simulator are combined with the layout editor environment. Applying this methodology to the memory device of sub-90nm design rule, we have validated that our methodology can capture the pattern failures at the full-chip level and optimize both the original layout and OPC rules of those areas.

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Section: Results Of Litho-friendly Layout Design and Model-based Opcmentioning

confidence: 99%

Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

et al. 2004

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“…We presented a full-chip, practical implementation of model-based, process and proximity compensation introduced in [1] and [2]. A two-dimensional etch model is employed.…”

Section: Resultsmentioning

confidence: 99%

“…Model-based correction was first applied to optical proximity because subwavelength imaging is the most distorting of these pattern transformations. Several researchers recognized that achieving tighter CD control required compensating patterning processes other than optical imaging and introduced the concept of process and proximity compensation (PPC) [1][2][3]. A chain (composition) of transformations can be inverted by using an end-to-end forward-model, from photomask data to etched pattern, and countering the distortion of the combined model.…”

Section: Introductionmentioning

confidence: 99%

Sequential PPC and process-window-aware mask layout synthesis

Sezginer¹,

Zach²,

Yenikaya³

et al. 2006

SPIE Proceedings

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We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.

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“…However, the conventional model-based OPC method has shown its limitation in the application for the etch process proximity correction since the fitting of optical simulation parameters cannot fully explain the loading effect resulting in large bias between the After Development Inspection (ADI) CD and the post etch feature dimension (ACI CD, After Cleaning Inspection CD). Several approaches to overcome this etch process proximity have been introduced for 150 nm ~ 120 nm technology nodes and proved to be effective for the memory devices having significant etch loading effects [6][7]. However the processes under sub-100nm design rules have faced the difficulties in the control of the large scale proximity factors such as flare effects and global loading effects [8][9].…”

Section: Introductionmentioning

confidence: 99%

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

et al. 2004

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Sub-wavelength lithography has made the OPC (Optical Proximity Correction) technology one of the most precious commodities for the fabrication of semiconductor devices. Highly accurate gate CD (Critical Dimension) control and design rule shrinkage have become possible through the development of the OPC technology. Nevertheless, the device specifications require more accurate gate CD control than the current OPC tools can cope with. For the model-based OPC to meet this tight CD specification, the model calibration is very important. Current model-based OPC tools use their OPC models which usually cover the full-chip area with one universal model calibrated by comparing the empirical CD with the simulated CD of specially designed test patterns. Despite its safety, a single model for the fullchip OPC is not accurate for 2-dimensional patterns, and does not take into account the long-range effects of the patterning process such as flare noise or macro loading effect which is closely related to the pattern density.In this work, we suggest a novel idea that applies the dual model to a single OPC process. We have found out that the CD trends of the patterns in the core region and peripheral region of a memory chip differ from each other so that it is difficult to apply the same model for both regions. For the 110 nm DRAM devices with 248nm lithography, we can reduce the gate CD variation up to 40% using the dual model OPC compared with the single model OPC. Since the dual model OPC uses two different models for a correction process, it should be carefully applied not to lose the conformity between the empirical process condition and the physical parameters of the models. The proposed dual model calibrated by the conservative modeling process reduces the gate CD variation by 50% compared with the single model OPC for a 90 nm DRAM device with 193nm lithography.

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Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node

Cited by 5 publications

References 0 publications

Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

Sequential PPC and process-window-aware mask layout synthesis

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

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