No abstract

Abstract-In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45 nm testcases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.Index Terms-Double patterning lithography (DPL), integer linear programming (ILP), layout decomposition, node splitting.

No abstract

Glucose deposition in peripheral tissue is an important parameter for the treatment of type 2 diabetes mellitus. The aim of this study was to investigate the effects of Spatholobus suberectus (Ss) on glucose disposal in skeletal muscle cells and additionally explore its in vivo antidiabetic potential. Treatment of ethanolic extract of S. suberectus (EeSs) significantly enhanced the glucose uptake, mediated through the enhanced expression of GLUT4 in skeletal muscle via the stimulation of AKT and AMPK pathways in C2C12 cells. Moreover, EeSs have potential inhibitory action on α-glucosidase activity and significantly lowered the postprandial blood glucose levels in STZ-induced diabetic mice, associated with increased expression of GLUT4 and AKT and/or AMPK-mediated signaling cascade in skeletal muscle. Furthermore, administration of EeSs significantly boosted up the antioxidant enzyme expression and also mitigated the gluconeogenesis enzyme such as PEPCK and G-6-Pase enzyme expression in liver tissue of STZ-induced diabetic mice model. Collectively, these findings suggest that EeSs have a high potentiality to mitigate diabetic symptoms through stimulating glucose uptake in peripheral tissue via the activation of AKT and AMPK signaling cascade and augmenting antioxidant potentiality as well as blocking the gluconeogenesis process in diabetic mice.

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies leads to dramatic increases in mask costs, pushing prototype and low volume production designs to the limit of economic feasibility. Multiple-Project Wafers (MPW), or "shuttle" runs, provide an attractive solution for such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs of the same technology flow. However, delay cost associated with schedule alignment is ignored in previous work. The savings on mask cost may be easily surpassed by the profit loss due to forced schedule alignment. Therefore, Multi-Flow Multi-Layer Multi-Project Reticles (MFMLMPR) become a more viable mask-cost saving technique for low volume production since mask cost is shared between different layers of the same design and between designs of different technology flows. However, MFMLMPR design introduces complexities not encountered in traditional single-flow or single-layer reticles. In this paper, we propose the first design flow for MFMLMPR aimed at minimizing the total manufacturing cost (including mask cost, wafer cost and delay cost) to fulfill given die production volumes. Our flow includes three main steps: (1) schedule-aware project partitioning with multi-flow embedding, (2) multi-frame reticle design, and (3) multi-project frame floorplanning. Our contributions are as follows. For the first step, a fast iterative matching algorithm is proposed to calculate the mask cost for multi-flow embedding with consideration of all practical manufacturing costs. We then propose an integer linear programming (ILP) based method for optimal manufacturing cost minimization. Since ILP suffers from impractically long runtimes when the number of projects is large, we propose a sliding time window heuristic to exhaustively search the solution space for the best tradeoff between mask cost and delay cost. For the second step, we propose an ASAP frame embedding heuristic to minimize the mask cost. Finally, for the third step, a "generalized chessboard" floorplan with simulated annealing is proposed to generate more dicing friendly frame floorplans for multi-flow projects, observing given maximum reticle sizes. We have tested our flow on production industry testcases. The experimental results show that our schedule-aware project partitioner yields an average reduction of 58.4% in manufacturing cost. The reduction of mask cost is around 46.3% compared with use of traditional layer-by layer checking methods. Our generalized chessboard floorplanner leads to an average reduction of 22.8% in the required number of wafers compared to the previous best reticle floorplanner.