Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers

Waris, Haroon; Wang, Chenghua; Liu, Weiqiang; Han, Jie; Lombardi, Fabrizio

doi:10.1109/tetc.2020.3013977

Cited by 34 publications

(16 citation statements)

References 13 publications

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“…However, multipliers ALM-SOA11 [23] and RAD1024 [9] with very low NMED outperform the proposed TL16-8/4 design. Similarly, the TL8-4/3 multiplier outperforms the DR-ALM4 [26] multiplier and the Ax8_3 [32] multiplier in terms of PSNR, but lags behind the Mitchell-trunc5-C1 [12] multiplier and the ALM-SOA11 [23] multiplier. Nevertheless, high MSSIM and acceptable PSNR indicate that the TL multipliers can replace the exact multiplier without a significant image quality decrease.…”

Section: A Image Smoothingmentioning

confidence: 92%

“…In [32], the authors proposed hybrid partial product-based building blocks by considering the probability distribution of the input operands. While [31] concentrated on simplification of Booth encoding, here, the authors focused on decomposing an 8-bit multiplier into 4-bit approximate multipliers.…”

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

“…We show the applicability of the TL16-8/4 multiplier and the TL8-4/3 multiplier in the image smoothing and the image classification with convolutional neural networks. In both applications, we compare the TL16-8/4 multiplier with the state-of-the-art approximate multipliers Mitchell-trunc6-C1, Mitchell-trunc8-C1, Mitchell-trunc6-C1UB, Mitchell-trunc8-C1UB [12], ILM-AA [15], ALM-SOA11 [23], DR-ALM4 [8], and RAD1024 [9] and the TL8-4/3 multiplier with the Mitchell-trunc5-C1, Mitchell-trunc5-C1UB [12], ALM-SOA4, ALM-SOA6 [23], DR-ALM3, DR-ALM4 [8] and Ax8_3 [32] multipliers.…”

Section: Application Case Studiesmentioning

confidence: 99%

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A Two-Stage Operand Trimming Approximate Logarithmic Multiplier

Pilipović

Bulić

Lotrič

2021

IEEE Trans. Circuits Syst. I

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We present an approximate logarithmic multiplier with two-stage operand trimming, which prioritises area and energy consumption while retains acceptable accuracy. The multiplier trims the least significant parts of input operands in the first stage and the mantissas of the obtained operands' approximations in the second stage. We evaluated the multiplier's efficiency in terms of error, energy, and area utilisation using NanGate 45nm. The experimental results show that the proposed multiplier exhibits smaller area utilisation and energy consumption than the state-of-the-art designs and that it behaves well in image processing and image classification with convolutional neural networks.

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Section: A Image Smoothingmentioning

confidence: 92%

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

Section: Application Case Studiesmentioning

confidence: 99%

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A Two-Stage Operand Trimming Approximate Logarithmic Multiplier

Pilipović

Bulić

Lotrič

2021

IEEE Trans. Circuits Syst. I

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“…We compare our work to state-of-the-art designs in the literature [13], [14], [20], [26], [36]- [40], and [42]. These are mostly approximate recursive proposals, but contributions from other fields are also considered.…”

Section: ×8 Approximate Multiplier Architecturesmentioning

confidence: 99%

“…In [40] the authors consider the probability distribution of the input operands to propose 4×4 multipliers, consisting of approximate NOR-based half adder and full adder designs. These elementary blocks are exploited to build approximate recursive multipliers.…”

Section: Introductionmentioning

confidence: 99%

Approximate Recursive Multipliers Using Low Power Building Blocks

Zacharelos

Nunziata

Saggese

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate results, rather than guaranteeing a correct outcome. Many contributions target the binary multiplier aiming to minimize the complexity of this common yet power-hungry circuit. Approximate recursive multipliers are low-power designs that exploit approximate building blocks to scale up to their final size. In this paper, we present two novel 4x4 approximate multipliers obtained by carry manipulation. They are used to compose 8x8 designs with different error-precision trade-off. The final circuits exhibit a competitive behavior in terms of error while reducing the power dissipation when compared to state-of-the-art proposals. The proposed multipliers and state-of-the-art designs found in the literature, have been synthesized targeting a 14nm FinFET technology to determine the electrical characteristics. Compared with an exact 8×8 multiplier, the least dissipative design proposed in this paper reduces power consumption and silicon area by 46%, and minimum delay by 21%. It also consumes 14% less power than the least power-hungry recursive circuit found in the literature, while offering 81% higher accuracy. Ιmage processing applications and a convolutional neural network are shown to demonstrate the effectiveness of the proposed multipliers.

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