A Two-Stage Operand Trimming Approximate Logarithmic Multiplier

Abstract

We present an approximate logarithmic multiplier with two-stage operand trimming, which prioritises area and energy consumption while retains acceptable accuracy. The multiplier trims the least significant parts of input operands in the first stage and the mantissas of the obtained operands' approximations in the second stage. We evaluated the multiplier's efficiency in terms of error, energy, and area utilisation using NanGate 45nm. The experimental results show that the proposed multiplier exhibits smaller area utilisation and energy consumption than the state-of-the-art designs and that it behaves well in image processing and image classification with convolutional neural networks.

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“…Multiplication is a very common, but expensive operation, with exact multipliers being large circuits that consume a significant amount of energy. Various approximate multipliers have been proposed in recent years [ 52 , 53 , 54 , 55 , 56 , 57 , 58 , 59 , 60 , 61 , 62 ]. Many studies reported that approximate multipliers behave well in neural network processing [ 56 , 59 , 60 , 61 , 63 , 64 , 65 ].…”

“…In the approximate multiplier design, we balanced accuracy and energy efficiency to suit the application’s needs. Various approximate multipliers have been proposed in recent years [ 54 , 55 , 56 , 57 , 58 , 59 , 60 , 61 , 62 ]. Approximate multipliers follow one of three design strategies: the approximate logarithmic design, the approximate nonlogarithmic design, and the hybrid design.…”

“…Approximate multipliers follow one of three design strategies: the approximate logarithmic design, the approximate nonlogarithmic design, and the hybrid design. Approximate logarithmic multipliers deliver a more straightforward design, but exhibit significantly higher computational error, while approximate nonlogarithmic multipliers have a lower computational error with the price of higher design complexity [ 54 , 61 ]. The hybrid multipliers combine both design strategies to balance accuracy and design complexity.…”

“…The dynamic range approximate logarithmic multiplier DR-ALM5 proposed by Yin et al [ 57 ] dynamically truncates the input operands and thus uses smaller bit-width logarithmic and antilogarithmic converters and adders to generate the product. Pilipović et al [ 61 ] proposed an approximate logarithmic multiplier with two-stage operand trimming (TL16-8/4), which trims the least significant parts of the input operands in the first stage and the mantissas of the obtained operands’ approximations in the second stage.…”

“…The scatter plot in Figure 2 , generated from the data obtained in [ 62 ], summarizes some of the state-of-the-art approximate multipliers in terms of standard comparison measures: power delay product (PDP) and normalized mean error distance (NMED) [ 61 ]. We can observe that more accurate nonlogarithmic multipliers consume more energy than logarithmic multipliers.…”