2022
DOI: 10.1109/mm.2022.3186547
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HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems

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Cited by 3 publications
(1 citation statement)
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“…For example, the matrix multiplication operator has a large number of different implementation methods in different chip architectures such as CPU and GPU, and the performance of the implementation methods is greatly different. The compilation system first performs hardware independent optimization on the computation graph [2], such as optimizing the memory arrangement and eliminating redundant nodes in the computation graph. Optimizations occur primarily in the form of operator calls or JIT compilations.…”
Section: Introductionmentioning
confidence: 99%
“…For example, the matrix multiplication operator has a large number of different implementation methods in different chip architectures such as CPU and GPU, and the performance of the implementation methods is greatly different. The compilation system first performs hardware independent optimization on the computation graph [2], such as optimizing the memory arrangement and eliminating redundant nodes in the computation graph. Optimizations occur primarily in the form of operator calls or JIT compilations.…”
Section: Introductionmentioning
confidence: 99%