An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration

Agostini, Nicolas Bohm; Curzel, Serena; Amatya, Vinay; Tan, Cheng; Minutoli, Marco; Castellana, Vito Giovanni; Manzano, Joseph; Kaeli, David; Tumeo, Antonino

doi:10.1145/3508352.3549424

Cited by 11 publications

(8 citation statements)

References 20 publications

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“…The SODA Synthesizer (Figure 1a) consists of two major components: i) SODA-OPT [2], the frontend compiler for system-level partitioning and high-level optimizations, and ii) PandA-Bambu [8], a state-of-the-art HLS tool.…”

Section: The Soda Synthesizermentioning

confidence: 99%

“…SODA-OPT [2] is the framework's compiler frontend (Figure 1b). It is developed by extending LLVM's MLIR, which allows to build a modular and reusable compiler infrastructure through the definition of dialects, i.e., specialized, and self-contained IRs compliant with MLIR's meta-IR syntax.…”

Section: Soda Frontendmentioning

confidence: 99%

“…SODA-OPT provides compilation passes to Search, Outline, Optimize, Dispatch, and Accelerate parts of the initial specification coming from high-level frameworks. SODA-OPT defines the soda MLIR dialect, used for the automatic partitioning of the input application into a host program responsible for orchestrating the runtime execution, and the custom hardware accelerators [2].…”

Section: Soda Frontendmentioning

confidence: 99%

“…Figure 2 provides an overview of signals and data incoming from a TEM instrument (1) and data that local instrument controller (2) and local analytics engine (3) process. In the experimental workflow, data might then be sent to a user facility (4) where additional analytics and control software are located.…”

Section: Precision Materials Synthesis Use Casementioning

confidence: 99%

“…To address some of these gaps, we introduced the Software Defined Accelerators (SODA) Synthesizer [3], an open-source, modular, and extensible end-to-end compiler-based framework for generating highly specialized hardware accelerators from algorithms designed in high-level programming frameworks. SODA is composed of SODA-OPT [2], a frontend based on the MultiLevel Intermediate Representation (MLIR) [11] framework, that interfaces with high-level programming frameworks and applies high-level optimizations, and PandA-Bambu [8], a state-of-the-art HLS tool that generates hardware designs in HDL (Verilog). SODA interfaces with external logic synthesis tools for FPGAs and ASICs.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

Castellana

Agostini

Limaye

et al. 2023

Proceedings of the 28th Asia and South Pacific Design Automation Conference

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The Software Defined Architectures (SODA) Synthesizer is an opensource compiler-based tool able to automatically generate domainspecialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows. CCS CONCEPTS• Hardware → High-level and register-transfer level synthesis.

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Section: The Soda Synthesizermentioning

confidence: 99%

Section: Soda Frontendmentioning

confidence: 99%

Section: Soda Frontendmentioning

confidence: 99%

Section: Precision Materials Synthesis Use Casementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

Castellana

Agostini

Limaye

et al. 2023

Proceedings of the 28th Asia and South Pacific Design Automation Conference

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Designing a Graphics Accelerator with Heterogeneous Architecture

Tarasov,

Mirzoyan,

Sovietov

2024

Communications in Computer and Information Science

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Modern High-Level Synthesis: Improving Productivity with a Multi-level Approach

Curzel

2024

Special Topics in Information Technology

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High-Level Synthesis (HLS) tools simplify the design of hardware accelerators by automatically generating Verilog/VHDL code starting from a general-purpose software programming language. Because of the mismatch between the requirements of hardware descriptions and the characteristics of input languages, HLS tools still require hardware design knowledge and non-trivial design space exploration, which might be an obstacle for domain scientists seeking to accelerate applications written, for example, in Python-based programming frameworks. This research proposes a modern approach based on multi-level compiler technologies to bridge the gap between HLS and high-level frameworks, and to use domain-specific abstractions to solve domain-specific problems. The key enabling technology is the Multi-Level Intermediate Representation (MLIR), a framework that supports building reusable compiler infrastructure. The proposed approach uses MLIR to introduce new optimizations at appropriate levels of abstraction outside the HLS tool while still relying on years of HLS research in the low-level hardware generation steps; users and developers of HLS tools can thus increase their productivity, obtain accelerators with higher performance, and not be limited by the features of a specific (possibly closed-source) backend. The presented tools and techniques were designed, implemented, and tested to synthesize machine learning algorithms, but they are broadly applicable to any input specification written in a language that has a translation to MLIR. Generated accelerators can be deployed on Field Programmable Gate Arrays or Application-Specific Integrated Circuits, and they can reach high energy efficiency without any manual optimization of the code.

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An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration

Cited by 11 publications

References 20 publications

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

Designing a Graphics Accelerator with Heterogeneous Architecture

Modern High-Level Synthesis: Improving Productivity with a Multi-level Approach

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