How to sort N items using a sorting network of fixed I/O size

Olariu, Stephan; Pinotti, Cristina M.; Zheng, S. Q.

doi:10.1109/71.770195

Cited by 23 publications

(16 citation statements)

References 25 publications

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“…For example, Tredennick [16] proposed architectural solutions for variable-length byte string processing. Similarly, Olariu [17] formally analyzed and proposed solutions for the problem of sorting arbitrary large number of items using a sorting network of small fixed I/0 size. Finally, ElGindy [18] investigated the problem of mapping recursive algorithms on reconfigurable hardware.…”

Section: Problem Formulationmentioning

confidence: 99%

Bringing High-Performance Reconfigurable Computing to Exact Computations

Ej-Araby

González

El‐Ghazawi

2007

2007 International Conference on Field Programmable Logic and Applications

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Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and/or floating-point computations. Exact computation, based on arbitrary-precision arithmetic, has been developed over the last decade as an emerging numerical computation paradigm in response to this problem of numerical non-robustness. Exact arithmetic, specifically arbitrary-precision arithmetic, has been traditionally implemented using efficient software libraries such as GNU Multi-Precision (GMP). However, this results in a slower arithmetic performance when compared to fixed-precision arithmetic. In this paper we present a first effort, to the best of our knowledge, of reconfigurable hardware support for arbitrary-precision arithmetic. The proposed hardware architectures are based on virtual convolution sche'duling which is derived from a formal representation of the problem. Targeting high performance and efficiency, dynamic (non-linear) pipelines techniques were exploited to eliminate the effects of deeply-pipelined operators. Referenced to GMP, our experiments showed promising results.

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Section: Problem Formulationmentioning

confidence: 99%

Bringing High-Performance Reconfigurable Computing to Exact Computations

Ej-Araby

González

El‐Ghazawi

2007

2007 International Conference on Field Programmable Logic and Applications

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“…Let us consider a sorting network of inputs . The number of the inputs defines the I/O size of the sorting network [4]. A sorting network consists of parallel channels, which can be thought of as wires carrying values, to which comparators are attached.…”

Section: Introductionmentioning

confidence: 99%

Sorting networks using L/sub p/ mean comparators for signal processing applications

Kotropoulos

Pappas

Pitas

2002

IEEE Trans. Signal Process.

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Digital implementations of sorting networks that rely on a digital signal processor core are not as efficient as their analog counterparts. This paper builds on the comparators for which efficient analog implementations exist that employ operational amplifiers. From a statistical point of view, comparators are based on nonlinear means. Their probability density function and the first-and second-order moments are derived for independent uniformly distributed inputs. comparators provide estimates of the minimum and maximum of their inputs. A proper approach to compensate for the estimation errors is proposed. Applications of the comparators in odd-even transposition networks, median approximation networks, and min/max networks are presented.

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“…Several AT 2 -optimal sorting networks under different word length models have been proposed in [7], [9], [15], and [17].…”

Section: (Atmentioning

confidence: 99%

Arbitrary long digit integer sorter HW/SW co-design

Cheng

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract--The coming of multimedia era and information security era indicates that must process longer digit integer data. Previous sort researches focus on pure performance of large amount of finite fixed digit/bit number. This paper discusses on effectively solving arbitrary long digit integer sorting problem by HW/SW co-design under the Area×Time 2 (AT 2 ) price-performance constraint. The work proposes multi-level (two-level) sort architecture to attain the object: an accomplished fixed-digit (k-bit) hardware sorter implements the first or basic level sorting, software programmed radix 2 k sort implements the second or higher level sorting. By Super Radix Sorting HW/SW co-design and reuse techniques, the work makes fixed-digit HW sorters more flexible and useful.

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How to sort N items using a sorting network of fixed I/O size

Cited by 23 publications

References 25 publications

Bringing High-Performance Reconfigurable Computing to Exact Computations

Bringing High-Performance Reconfigurable Computing to Exact Computations

Sorting networks using L/sub p/ mean comparators for signal processing applications

Arbitrary long digit integer sorter HW/SW co-design

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