Bringing High-Performance Reconfigurable Computing to Exact Computations

Ej-Araby, E.; González, Iván; El‐Ghazawi, Tarek

doi:10.1109/fpl.2007.4380629

Cited by 8 publications

(3 citation statements)

References 19 publications

(15 reference statements)

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“…E. El-Araby proposed the use of High Performance Reconfigurable Computers (HPRCs) as a promising candidate for arbitrary precision arithmetic [10]. F.T.…”

Section: Introductionmentioning

confidence: 99%

“…Field-programmable gate array (FPGA) chips, which operate at the bit level and serve as custom hardware for the different computation precisions, could potentially implement high precision scientific computing applications and provide significantly higher performance than a generalpurpose CPU [10], [18], [19]. The computational capability of FPGAs is increasing rapidly.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic

Lei

Dou

Zhou

2011

IEICE Trans. Inf. & Syst.

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SUMMARYMany scientific applications require efficient variableprecision floating-point arithmetic. This paper presents a special-purpose Very Large Instruction Word (VLIW) architecture for variable precision floating-point arithmetic (VV-Processor) on FPGA. The proposed processor uses a unified hardware structure, equipped with multiple custom variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved through the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. We take division and exponential function as examples to illustrate the design of variable-precision elementary algorithms in VV-Processor. Finally, we create a prototype of VV-Processor unit on a Xilinx XC6VLX760-2FF1760 FPGA chip. The experimental results show that one VV-Processor unit, running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 5X-37X for basic variable-precision arithmetic operations and elementary functions.

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“…E. El-Araby proposed the use of High Performance Reconfigurable Computers (HPRCs) as a promising candidate for arbitrary precision arithmetic [10]. F.T.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic

Lei

Dou

Zhou

2011

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…Achieved accelerations in this case are in the range of ten to several hundreds of times. In this area, reconfigurability has also been exploited for high performance computing [4] and all kinds of adaptive filtering for DSP processing, for instance the adaptive FIR filter presented in [5].…”

Section: Introductionmentioning

confidence: 99%

Using partial reconfiguration for SoC design and implementation

et al. 2009

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Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned.This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the paper.

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