FPGA Implementation of Variable-Precision Floating-Point Arithmetic

Lei, Yuanwu; Dou, Yong; Guo, Song; Zhou, Jie

doi:10.1007/978-3-642-24151-2_10

Cited by 10 publications

(4 citation statements)

References 18 publications

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“…VPFPAP [17] (similar to VV in [32]) adopts a different scheme for the Kulisch architecture: the processor exposes the elementary operations on mantissa segments (again 64bit wide). The software is responsible for sequencing these elementary operations, and exploits 64 entries of internal memory to store the intermediate results.…”

Section: Fpu Architectures For Extended Precisionmentioning

confidence: 99%

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Guthmuller,

Fuguet,

Bocco

et al. 2024

IEEE Trans. Comput.

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A key concern in the field of scientific computation is the convergence of numerical solvers when applied to large problems. The numerical workarounds used to improve convergence are often problem specific, time consuming and require skilled numerical analysts. An alternative is to simply increase the working precision of the computation, but this is difficult due to the lack of efficient hardware support for extended precision. We propose Xvpfloat, a RISC-V ISA extension for dynamically variable and extended precision computation, a hardware implementation and a full software stack. Our architecture provides a comprehensive implementation of this ISA, with up to 512 bits of significand, including full support for common rounding modes and heterogeneous precision arithmetic operations. The memory subsystem handles IEEE 754 extendable formats, and features specialized indexed loads and stores with hardware-assisted prefetching. This processor can either operate standalone or as an accelerator for a general purpose host. We demonstrate that the number of solver iterations can be reduced up to 5× and, for certain, difficult problems, convergence is only possible with very high precision (≥384 bits). This accelerator provides a new approach to accelerate large scale scientific computing.

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Section: Fpu Architectures For Extended Precisionmentioning

confidence: 99%

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Guthmuller,

Fuguet,

Bocco

et al. 2024

IEEE Trans. Comput.

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“…Thus, algorithms that can benefit from instruction-level parallelism via deep pipelining tend to display significant performance improvement from an FPGA implementation. Furthermore, the flexible logic of an FPGA can accelerate scientific application by configuring the hardware to perform variable-precision floating point arithmetic 108 or simply fixed-point arithmetic, instead of traditional single-or double-precision. For example, Gothandaraman et al 109 accelerated a Quantum Monte Carlo (QMC) chemistry application by using FPGA logic to set up fixed-precision arithmetic and to create parallel and pipelined architectures to perform the potential energy and wave function calculations in the QMC algorithm.…”

Section: Emerging Hardware Trendsmentioning

confidence: 99%

Novel Computer Architectures and Quantum Chemistry

et al. 2020

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Electronic structure theory (especially quantum chemistry) has thrived and has become increasingly relevant to a broad spectrum of scientific endeavors as the sophistication of both computer architectures and software engineering has advanced. This article provides a brief history of advances in both hardware and software, from the early days of IBM mainframes to the current emphasis on accelerators and modern programming practices.

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“…Unfortunately, these processor designs are only specified and simulated at the behavioural level, and no physical implementation has been made. In [15], a special-purpose very large instruction word processor for variable-precision arithmetic is presented, which uses unified hardware to implement various algebraic and transcendental functions. Its performance is obtained by using the explicitly parallel nature of the very large instruction word and dynamically varying the precision of intermediate computations.…”

mentioning

confidence: 99%

“…Up to now, none of the MPA processor/coprocessor results [13][14][15][16][17][18][19][20] presented in the literature have gained either immense popularity or worldwide success. In our opinion, it stems partially from the fact that none of those solutions are freely available as an open-source intellectual property (IP) core.…”

mentioning

confidence: 99%

Open-Source Coprocessor for Integer Multiple Precision Arithmetic

Rudnicki¹,

Stefański

Żebrowski³

2020

Electronics

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This paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore, it can be implemented within field programmable gate arrays (FPGAs) at various scales, e.g., within a system on chip (SoC), combining CPU cores and FPGA within a single chip as well as FPGA acceleration cards. The coprocessor handles integer numbers with precisions in the range 64 bits–32 kbits, with the limb size set to 64 bits. In our solution, the sign-magnitude representation is used to increase the efficiency of the multiplication operation as well as to provide compatibility with existing software libraries for MPA. The coprocessor is benchmarked in factorial ( n ! ), exponentiation ( n n ) and discrete Green’s function (DGF) computations on Xilinx Zynq-7000 SoC on TySOM-1 board from Aldec. In all benchmarks, the coprocessor demonstrates better runtimes than a CPU core (ARM Cortex A9) executing the same computations using a software MPA library. For sufficiently large input parameters, our coprocessor is up to three times faster when implemented in FPGA on SoC, rising to a factor of ten in DGF computations. The open-source coprocessor code is licensed under the Mozilla Public License.

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FPGA Implementation of Variable-Precision Floating-Point Arithmetic

Cited by 10 publications

References 18 publications

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Novel Computer Architectures and Quantum Chemistry

Open-Source Coprocessor for Integer Multiple Precision Arithmetic

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