How to control defect formation in monolithic III/V hetero-epitaxy on (100) Si? A critical review on current approaches

Abstract

The monolithic hetero-integration of III/V materials on Si substrates could enable a multitude of new device applications and functionalities which would benefit from both the excellent optoelectronic properties of III/V compound materials and the well-established and highly mature Si manufacturing technologies. Due to the lattice mismatch between most III/V compound semiconductors and Si substrates, monolithic growth inevitably leads to the formation of strain releasing defects which degrade the final device performance and reliability. This review paper provides an overview of current approaches and methods to control the defect formation in monolithic III/V hetero-epitaxy on (001) Si substrates. The focus is on understanding the mechanisms of defect nucleation, manipulation and confinement in order to eventually realize active III/V device layers on Si substrates with high crystalline quality. For details about device applications numerous references are listed. Although many different integration approaches are discussed in the literature, there are two main concepts for the hetero-epitaxial growth of III/V material on Si: growth on blanket Si wafers and selective area growth on patterned Si substrates. Both methods have their advantages and disadvantages with respect to defect control and could potentially enable the integration of different III/V devices on a Si platform.

Nano-Ridge Engineering of GaSb for the Integration of InAs/GaSb Heterostructures on 300 mm (001) Si

“…It is a scanning electron microscopy (SEM) based technique, which uses the strong dependency of the backscattered electron intensity on the local crystal properties (lattice plane orientation, presence of strain fields, etc.). The inspection method is non-destructive and visualizes individual defects on a smooth sample surface including a 3-dimensional structure like a NR [12,45,46]. Planar defects can be identified as a contrast line, whereas a threading dislocation, which is a 1-dimensional line defect, gives a dot-like contrast feature in the ECCI image.…”

“…As optoelectronic device performance degrades quickly with the presence of relaxation defects, it is important to achieve a high crystal quality in the active device area and to separate the latter clearly from the region of plastic relaxation. Different methods have been investigated to reduce the defect density in the active layer stack, e.g., the growth of a thick metamorphic buffer or the implementation of defect filter layers such as strained layer superlattices [4,[12][13][14].…”

“…If this IMF array releases the entire strain in the III-Sb heterofilm, no micrometer thick buffer layer on Si is needed to reduce the defect density, which is a significant advantage for device co-integration on a silicon photonics platform. Balakrishnan et al [22] claimed a threading defect density of about 1 × 10 6 cm −2 after the deposition of around 1 µm AlSb/GaSb on Si [12]. Relaxation via an IMF array is also possible for GaSb deposited on GaAs substrates, although the lattice mismatch is only 7.8%.…”

“…A fundamentally different approach to control plastic relaxation in III-V heteroepitaxy on Si is selective area growth (SAG) in highly confined patterns [12,[24][25][26]. In particular, the III-V growth in trenches with a high aspect ratio (AR) (trench height/trench width) is of great interest for photonic applications in the C-and O-band [27][28][29].…”

“…In particular, the III-V growth in trenches with a high aspect ratio (AR) (trench height/trench width) is of great interest for photonic applications in the C-and O-band [27][28][29]. Dislocation defects are blocked at the side wall of the pattern by aspect ratio trapping (ART) [12], and the III-V ridge lines serve as waveguides which simplify the light coupling into passive waveguides [30]. Usually, the trench pattern is fabricated utilizing a silicon oxide (SiO 2 ) layer on top of a Si wafer or a SOI substrate.…”