HotSpot : Visualizing dynamic power consumption in RTL designs

English, Tom; Man, Ka Lok; Popovici, Emanuel; Schellekens, Michel

doi:10.1109/ewdts.2008.5580137

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…It aims at design optimization for power at the RTL stage itself, where there is maximum scope for power savings. It also overcomes the limitation of the above mentioned presynthesis technique [5].…”

Section: B Shortcoming Of Existing Techniques and A"fix"mentioning

confidence: 98%

“…One such technique, finding hotspots in the design based on the switching activity of different nodes using RTL simulation, has been proposed by English, Man, Popovici and Schellekens [5]. This technique does a good job in finding zones in the circuit design which show high switching activity and hence higher dynamic power consumption.…”

Section: B Shortcoming Of Existing Techniques and A"fix"mentioning

confidence: 98%

“…Development of new design and verification methodologies which could potentially unearth timing and power related issues early in the design flow is gaining in importance [4]. This presents a motivating challenge to VLSI researchers, R&D teams of semiconductor companies, and EDA vendors all over the world to come up with innovative solutions which make the RTL -Design & Verification not just functionally correct but 'Aware and Smart' in terms of anticipating power related issues which might occur later in the design flow, thereby reducing the time-to-market cycle [5].…”

Section: Introductionmentioning

confidence: 99%

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Fixing power bugs at RTL stage using PSL assertions

Purdy

Singh

Seli

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Power dissipation has now become the most critical design constraint. In the design flow of an SoC, power estimation and analysis usually come into the picture only after the completion of RTL synthesis. However, design optimization for low power is most suitable before synthesis. Each decrease in process geometry makes dynamic power targets harder to achieve. Also, changes made later in the design for power optimization lead to costly re-spin. It is better to pin-point power related problems in the design as early as possible when they can still be fixed. This also reduces risk by ensuring that the design meets power goals before embarking on its implementation. Our novel approach presented in this paper introduces power analysis at the RTL stage itself, using PSL assertions. This enables the SoC designer to optimize the design from a low power perspective at a very early stage (RTL) in the design flow, where the scope of modification is maximized and the cost minimized.

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Section: B Shortcoming Of Existing Techniques and A"fix"mentioning

confidence: 98%

Section: B Shortcoming Of Existing Techniques and A"fix"mentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fixing power bugs at RTL stage using PSL assertions

Purdy

Singh

Seli

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…This model forms the basis of more elaborate, block-based models, such as English et al [2008], Huang et al [2004], Noda et al [2010], and Pedram and Nazarian [2006]. Such models can be used to reflect the fluctuations of temperature distribution across the die.…”

Section: Temperature Profilementioning

confidence: 99%

Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation

Hatami

Baranowski

Prinetto

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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As the technology shrinks, nonfunctional properties (NFPs) such as reliability, vulnerability, power consumption, or heat dissipation become as important as system functionality. As NFPs often influence each other, depend on the application and workload of a system, and exhibit nonlinear behavior, NFP simulation over long periods of system operation is computationally expensive, if feasible at all.This article presents a piecewise evaluation method for efficient NFP simulation. Simulation time is divided into intervals called evaluation windows, within which the NFP models are partially linearized. High-speed functional system simulation is achieved by parallel execution of models at different levels of abstraction. A trade-off between simulation speed and accuracy is met by adjusting the size of the evaluation window.As an example, the piecewise evaluation technique is applied to analyze aging caused by two mechanisms, namely Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), in order to identify reliability hotspots. Experiments show that the proposed technique yields considerable simulation speedup at a marginal loss of accuracy.

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“…This will be achieved by annotating power consumption information from simulation as TinyOS applications (e.g. using Power- TOSSIM/VMNet) onto a PPTA of the WSN design (see also [26] for details). Figure 1 provides an example of NetTopo user interface that presents the WSN topology and visualise the subset of nodes those discriminate certain criteria.…”

Section: Software Development In Tepawsn 1) Simulation Verificatimentioning

confidence: 99%