Power dissipation has now become the most critical design constraint. In the design flow of an SoC, power estimation and analysis usually come into the picture only after the completion of RTL synthesis. However, design optimization for low power is most suitable before synthesis. Each decrease in process geometry makes dynamic power targets harder to achieve. Also, changes made later in the design for power optimization lead to costly re-spin. It is better to pin-point power related problems in the design as early as possible when they can still be fixed. This also reduces risk by ensuring that the design meets power goals before embarking on its implementation. Our novel approach presented in this paper introduces power analysis at the RTL stage itself, using PSL assertions. This enables the SoC designer to optimize the design from a low power perspective at a very early stage (RTL) in the design flow, where the scope of modification is maximized and the cost minimized.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.