Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with highperformance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative "hybrid" architectures with hardware acceleration. In this paper, we survey existing solutions and describe how FPGAs are being used in electronic trading to approach the goal of zero latency. We present an FPGA IP library which implements networking, I/O, memory interfaces and financial protocol parsers. The library provides pre-built infrastructure which accelerates the development and verification of new financial applications. We have developed an example financial application using the IP library on a custom 1U FPGA appliance. The application sustains 10Gb/s Ethernet line rate with a fixed end-toend latency of 1µs -up to two orders of magnitude lower than comparable software implementations.
We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF (2 251 ). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.
As part of our ongoing research, we present BSAA -Bus Switching Activity Analyser -a CAD tool which reads switching activity from RTL simulation, extracting a list of the circuit's buses and associated switching activity metrics. The list is filtered and sorted according to user-specified criteria, producing reports and a set of graphical switching activity profiles of the circuit's most active buses. The tool identifies common profiles corresponding to typical address-and data bus traffic. As part of a CAD flow, BSAA enables rapid switching activity analysis and encoding design for switching minimisation on heavily-loaded cross-chip buses and IO pins.
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