Hot-Carrier Photoemission in Scaled CMOS Technologies: A Challenge for Emission Based Testing and Diagnostics

Tosi, Alberto; Stellari, Franco; Pigozzi, A.; Marchesi, Giulio; Zappa, Franco

doi:10.1109/relphy.2006.251284

Cited by 22 publications

(10 citation statements)

References 19 publications

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“…However, the actual emission probability is complex to calculate as many factors contribute [134]. Scaling, for example, has some positive effects on the emission probability [169], which makes it possible to observe hot-carrier luminescence even in recent technologies.…”

Section: Photonic Emission In Cmosmentioning

confidence: 99%

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Why cryptography should not rely on physical attack complexity

Krämer

2016

It - Information Technology

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Ich versichere an Eides statt, dass ich diese Dissertation selbständig verfasst und nur die angegebenen Quellen und Hilfsmittel verwendet habe. Datum Für meine Eltern AbstractEver since the first side channel attacks and fault attacks on cryptographic devices were introduced in the mid-nineties, new possibilities of physical attacks have been consistently explored. The risk that these attacks pose is reduced by reacting to known attacks and by developing and implementing countermeasures against them. For physical attacks whose theory is known but which have not been conducted yet, however, the situation is different. Attacks whose physical realization is assumed to be very complex are taken less seriously. The trust that these attacks will not be realized due to their physical complexity means that no countermeasures are developed at all. This leads to unprotected devices once the assessment of the complexity turns out to be wrong.This thesis presents two practical physical attacks whose theory is known for several years. Since neither attack has previously been successfully implemented in practice, however, they were not considered a serious threat. Their physical attack complexity has been overestimated and the implied security threat has been underestimated. First, we introduce the photonic side channel, which offers not only temporal resolution, but also the highest possible spatial resolution. Due to the high cost of its first realization, it has not been taken seriously. We show both simple and differential photonic side channel analyses. Then, we present a fault attack against pairing-based cryptography. Due to the need for at least two independent precise faults in a single pairing computation, it has also not been taken seriously. We show how attackers can reveal the secret key of symmetric as well as asymmetric cryptographic algorithms based on these physical attacks. We present countermeasures on the software and the hardware level, which help to prevent these attacks in the future.Based on these two presented attacks, this thesis shows that the assessment of physical attack complexity is error-prone. Hence, cryptography should not rely on it. Cryptographic technologies have to be protected against all physical attacks, have they already been realized or not. The development of countermeasures does not require the successful execution of an attack but can already be carried out as soon as the principle of a side channel or a fault attack is understood.

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Section: Photonic Emission In Cmosmentioning

confidence: 99%

“…eliminate optical emission [161,169,171]. Moreover, photonic detection techniques continue to improve rapidly.…”

Section: Simple Photonic Emission Analysis 57/136mentioning

confidence: 99%

Why cryptography should not rely on physical attack complexity

Krämer

2016

It - Information Technology

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“…TRE emission intensity decreases nonlinearly with supply voltage (Rowlette and Eiles, 2003). The resulting SNR challenge of recent IC technologies may not be overly severe as recent studies indicate (Tosi et al, 2006). Spectral information of the emission has so far only marginally been used in analysis.…”

Section: Time Resolved Photon Emission (Tre)mentioning

confidence: 99%

Physical IC debug – backside approach and nanoscale challenge

et al. 2008

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Abstract. Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50-100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach.

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“…Exponentially decreasing PE intensity with supply voltage has for a long time been regarded as main risk for the future application of this technique. But, recent studies at low voltage technology devices [9] indicate that the resulting SNR challenge may not be overly severe. The main challenges of PE and TRE are: -The internal delay per inverter will go below the TRE time resolution in the coming years which makes it more complicted to associate a definite device to a switching event.…”

Section: Photon Emissionmentioning

confidence: 99%

Scale, function and materials: debug and diagnosis in electronic device technology roadmap

Boit

2008

2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Debug and Diagnosis of Integrated Circuits with physical techniques is necessarily correlated strongly to the innovation of electronic device technology. Miniaturization and scaling were main reasons for the introduction of signal access through chip backside in recent years. The introduction of new materials is adding critical challenges, even on the active device level. Based on the technology roadmap to 32nm and below, this article presents the boundary conditions for functional device analysis and discusses the analysis options. The potential of established techniques is assessed with respect to the mismatch of optical resolution and nanoscale device dimensions, to the resolution gain of scanning probe techniques vs. working distance requirements, to the FIB techniques for circuit edit and ultra thin silicon preparation. Applications of innovative approaches are demonstrated, and critical issues like thermal / mechanical management are discussed.

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Hot-Carrier Photoemission in Scaled CMOS Technologies: A Challenge for Emission Based Testing and Diagnostics

Cited by 22 publications

References 19 publications

Why cryptography should not rely on physical attack complexity

Why cryptography should not rely on physical attack complexity

Physical IC debug – backside approach and nanoscale challenge

Scale, function and materials: debug and diagnosis in electronic device technology roadmap

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