DC-Step-Stress-Tests of GaN HEMTs have been performed on wafers with and without GaN-cap.The tests consist of a step ramping of drain-source voltage V DS by 5V every two hours at off-state. The irreversible evolution of leakage current starting at a certain drain voltage has been taken as a criterion for the onset of device degradation. It has been stated that there is a stability limit for V DS depending on the epitaxial design. It has been found that wafers with GaN cap show much higher critical voltages as compared to non-capped epitaxial designs. Electroluminescence measurements have been performed to localize defects after DC-Step-Stress-Tests up to 80V for wafer without GaN cap and 120V for wafer with GaN cap.
TEMPEIWIIJRE ORADIENT -SEI (Seebeck Effect Imaging) generated by TLS (Thermal Laser Stimulation) has proven to be a very powerful tool for open circuit localization in microelectronics and is a common tool in FA laboratories. Although the basic Seebeck Effect (SE) is understood well, the interpretation of some results remained unsolved especially under hiss voltage or in complex smctures like ICs. A parametric investigation of SE in passive devices of various resistances is presented, and infannation about SE in active devices is provided.The results are interpreted taking into account that SE is never the only effect which is produced by T U . With the contribution of SE together with the conventional Optical Beam Induced Resistance CHmge (OBIRCH) in interconnects and contacts, this systematic approach based on device simulation represents the full variety of SEI phenomena, in constant current and constant voltage condition.Constant current is the regular SE1 operation mode and should be used whenever possible as the SE signal does not depend on device resistance. In ICs though, usually constant voltage is mandatory.
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