Hot carrier degradation in LDMOS power transistors

Cheng, Chien-Fu; Wu, Janne-Wha; Lee, C.C.; Shao, J.H.; Wang, T.

doi:10.1109/ipfa.2004.1345626

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…Because of the photolithgraphy alignment error, the device turn-on voltage relative drift gradually rises as the parameter A decreases. And due to the Kirk effect [9] , reducing the n-drift implant dose causes the nLEDMOS safe operating area (SOA) to shrink under typical gate bias condition (V gs = 5 V). Thus these two layout and process key parameters need to be compromised alongside the device turn-on voltage stability, E-SOA (electric safe operating area) and HC-SOA (hot carrier safe operating area).…”

Section: Measurement and Discussionmentioning

confidence: 99%

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Qian

Sun

et al. 2009

J. Semicond.

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Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO 2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

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Section: Measurement and Discussionmentioning

confidence: 99%