Layout and process hot carrier optimization of HV-nLEDMOS transistor

Abstract

Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO 2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

Optimization of lateral double-diffused MOS transistors in 0.18 µm bipolar-CMOS-DMOS technology for wide-voltage applications

“…Of these, the LDMOS device is the key element used in the power device of the BCD process. In order to reduce the chip area and power consumption, it would be better to reduce the on-state resistance (R on ) in the identical operating voltage, and in order to guarantee the reliability of chip, it would be important to secure the safe operating area (SOA) [7,8]. This study will discuss the characteristics and optimization of the n-LDMOS, which is implemented in the 0.18 μm BCD process.…”