History Index of Correct Computation for Fault-Tolerant Nano-Computing

Dotan, Yocheved; Levison, Nadav; Avidan, R.; Lilja, David J.

doi:10.1109/tvlsi.2008.2012014

Cited by 8 publications

(2 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a result, designers will have to devise a method for operating with defective structures, given that all the structures will have defects. In [41], the authors introduce the concept of history voting. The history index of each of the redundant units is incremented by 1 when its computation is identical to that of the majority and is decremented by 1 when it is not.…”

Section: Related Workmentioning

confidence: 99%

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Oughali

2014

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Related Workmentioning

confidence: 99%

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Oughali

2014

Microelectronics Reliability

View full text Add to dashboard Cite

“…With the very high defect rates associated with nanoscale manufacturing, various strategies need to be applied for reliable manufacturing of the particular nano computational fabric. Different approaches such as built-in defect tolerance [5] [6] and reconfiguration [7] [8] have been explored for emerging nano-computational fabrics to achieve fault tolerance [9] [10]. Built-in fault tolerance techniques do not need complex micro-nano interfacing, special reconfigurable devices or defect map extraction.…”

Section: Introductionmentioning

confidence: 99%

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Vijayakumar

Narayanan

Koren

et al. 2010

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

View full text Add to dashboard Cite

Emerging nano-device based architectures are expected to experience high defect rates associated with the manufacturing process. In this paper, we introduce a novel built-in heterogeneous fault-tolerance scheme, which incorporates redundant circuitry into the design to provide fault tolerance. A thorough analysis of the new scheme was carried out for various system level metrics. The implementation and analysis were carried out on WISP-0, a stream processor implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) fabric. We show that intelligent assignment of redundancy levels and nanoscalevoting strategies across WISP-0 greatly improves area, effective yield and performance for the nano-processor. The new scheme outperforms homogeneous schemes for a defect range of 3% to 9.75% where the metric used is the product of performance and effective yield.

show abstract