Highly robust oxide TFT with bulk accumulation and source/drain/active layer splitting

The flexibility, strength, and smoothness of amorphous metal thin-films have enabled the development of a new generation of high-performance diode and transistor devices for flat panel and thin-film electronic applications. This work reports on recent progress toward the development of amorphous metal thin-film transistors. The etch stop layer type transistors reported in this work demonstrate field effect mobilities as high as 20 cm 2 /V s, depending on the processing conditions. All thin-film layers for these amorphous metal thin-film transistors were deposited using sputter physical vapor deposition techniques at room temperature. The low temperature processing, as well as the strong and flexible nature of amorphous metals, makes amorphous metal thin-film transistor technology potentially useful for robust high-speed highly flexible electronics.

Section: Resultsmentioning

confidence: 99%

P‐196: Late‐News‐Poster: Low‐Temperature All Sputter IGZO‐TFT Fabricated with Amorphous Metal Thin‐Films

Kearney¹,

Mendez²,

Self³

et al. 2020

“…Recently bulk accumulation has come to the forefront in the development of amorphous oxide semiconductors (AOS) like a-IGZO TFTs, as improvements in field effect mobility have been reported (3). The concept of "bulk accumulation" corresponds to TFT devices whose accumulation layer thickness (tACC) is similar to that of the physical thickness of the semiconductor layer (4)(5)(6). In order to determine if a device can achieve bulk accumulation, the Debye length (λD) must first be known as it is a key physical parameter for determining the maximum accumulation layer thickness (7,8), see Equation 1.…”

Section: Introductionmentioning

confidence: 99%

43.2: Parasitic Capacitance Model for BGTC TFTs and Verification Using C‐V Measurements from Devices with Various Channel Dimensions

Mendez¹

2023

A model of the accumulation and depletion capacitance for a bottom gate top contact (BGTC) thin film transistors (TFT) with an etch stop layer (ESL) was presented. The model, which includes the parasitic capacitance due to device layout, was verified by comparison of measured data and modeled data for TFTs of various dimensions. Good agreement was seen between measured and modeled data, where the model underestimated the capacitance by 2% to 7%, depending on the device dimensions. The impact of the parasitic capacitance on estimates of the Debye length (λD ) are discussed and it is demonstrated that the relative error in the λD estimates is directly proportional to the ratio of the parasitic capacitance over the measured capacitance (CPAR/CM). The relative error was shown to increase as the ratio increases, leading to a larger underestimation of the λD. It was concluded that the parasitic capacitance to measured capacitance should be minimized for devices that are used for extraction of physical parameters from C‐V data. This is especially important in the case where the λD is a critical parameter in the optimization of TFT performance.

“…To address some limitations of conventional structures and materials, TFT architectures have been developed having more than one control terminal (gate). Currently, gates opposing each other on either side of the semiconductor layer are used to electrically tune the threshold voltage of transistors ("back gate" concept) [8], and even to increase the current density in the onstate by confining charge transport away from interfaces (bulk accumulation) [9]. Separately, auxiliary electrodes which are either coplanar to or opposite the gate have been utilized to preferentially control carrier type in ambipolar semiconductors [10], or to increase the efficiency of optoelectronic devices.…”

Section: Introductionmentioning

confidence: 99%

31‐1: Invited Paper: The Multimodal Thin‐Film Transistor (MMT): A Versatile Low‐Power and High‐Gain Device with Inherent Linear Response

Bestelink

Sagazan

Bateson

et al. 2020