Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Ueki, Makoto; Narihiro, M.; Ohtake, Hiroto; Tsuji, Masayoshi; Tada, Munehiro; Ito, Fuminori; Harada, Y.; Abe, Mari; Inoue, N.; Arai, Ken‐ichi; Takeuchi, T.; Saito, Shinobu; Onodera, T.; Furutake, N.; Hiroi, Masayuki; Sekine, Makoto; Hayashi, Y.

doi:10.1109/vlsit.2004.1345393

Cited by 11 publications

(7 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The gas pressure was 25 mtorr, the gap between the electrodes was 35 mm, and the substrate temperature was 20 C. An N CHF -based gas chemistry with a small amount of oxygen, instead of a C F Ar mixture gas [16], [17], was selected [18] to increase the etching selectivity of the SiOCH films to the SiO HM. The ratio of nitrogen to CHF was fixed at 1:1, and the dependence of etching rates on oxygen flow was determined.…”

Section: Methodsmentioning

confidence: 99%

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Ohtake

Tsuji

Tada

et al. 2006

IEEE Trans. Semicond. Manufact.

Self Cite

View full text Add to dashboard Cite

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film ( = 2 6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid ( = 2 9) or porous ( = 2 6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O 2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multihard-mask process for the DD structure in porous SiOCH film with no exposure to O 2 -ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond.Index Terms-Author, please supply your own keywords or send a blank e-mail to keywords@ieee.org to receive a list of suggested keywords.

show abstract

Section: Methodsmentioning

confidence: 99%

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Ohtake

Tsuji

Tada

et al. 2006

IEEE Trans. Semicond. Manufact.

Self Cite

View full text Add to dashboard Cite

show abstract

“…5) For further reduction of C int , the porous low-k SiOCH materials (k < 2:7) have been introduced into the manufacturing since 65-nm-node. 6,7) However, the porous low-k SiOCH materials are likely damaged in the plasma process such as dry etching and some surface treatments. The damaged porous low-k SiOCH film degrades the interconnects performances such as C int , electro-migration (EM), stress induced voiding (SiV) and time dependent dielectric breakdown (TDDB) due to mainly moisture absorption into hydrophilic damaged layer.…”

Section: Introductionmentioning

confidence: 99%

“…The damaged porous low-k SiOCH film degrades the interconnects performances such as C int , electro-migration (EM), stress induced voiding (SiV) and time dependent dielectric breakdown (TDDB) due to mainly moisture absorption into hydrophilic damaged layer. [6][7][8][9][10] Moreover, the porous SiOCH film has low modulus and weak adhesive strength with SiCN cap film, degrading reliability in chip packaging interaction (CPI). [11][12][13][14][15][16] In order to prevent such degradations of interconnect performances, SiO 2 hard mask (HM), etch stop layer (ES), and the hybrid structure with porous low-k materials as the IMD films and rigid low-k materials as the ILD films have been investigated.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13][14][15][16] In order to prevent such degradations of interconnect performances, SiO 2 hard mask (HM), etch stop layer (ES), and the hybrid structure with porous low-k materials as the IMD films and rigid low-k materials as the ILD films have been investigated. [6][7][8][9][10][17][18][19][20][21][22][23] However, the introduction of such higher-k materials causes the increase of effective k-value (k eff ), which is derived from comparison between measured C int and calculated C int by assuming the uniform k eff material for all dielectrics such as IMD, ILD, hard mask (HM), and cap layer. So, the k eff reduction with maintaining the reliabilities is a key to introduce porous low-k SiOCH materials into IMD and ILD.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Effects of Low-k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Tsuji

Inoue

Ueki

et al. 2012

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Low capacitance and highly reliable Cu dual-damascene (DD) interconnects have been developed with self-organized “seamless low-k SiOCH stacks” (SEALS) structure. A carbon-rich sub-nano porous SiOCH (k=2.5) was directly stacked on an oxygen-rich porous SiOCH (k=2.7) in the SEALS structure, without a hard-mask (HM) and etch-stop (ES) layer of SiO2. The effective k-value (k eff) of the Cu DD interconnect including the SiCN capping layer (k=4.9) was reduced to 2.9 compared to 3.4 on a conventional hybrid structure with SiO2-HM and ES, which had been used in 65-nm-node mass production. The interconnect delay of a 45-nm-node complementary metal oxide semiconductor (CMOS) ring oscillator (RO) was reduced by 15% referring to that of the conventional hybrid structure. Interconnect reliabilities, such as the interline time dependent dielectric breakdown (TDDB) and thermal cycles, were unchanged from those of the conventional hybrid interconnects. No failure was detected for chip package interaction (CPI) during reliability tests in a plastic ball grid array (PBGA) package. SEALS is a promising structure for scaled down ultra large scale integrations (ULSIs) for highly reliable and high speed operation, and low power consumption.

show abstract

“…Currently, wide varieties of low-k dielectrics isolate between fine-pitched interconnects to reduce the parasitic capacitance in the advanced LSI technology. [1][2][3][4] The low interconnect capacitance suppresses the signal propagation delay, power consumption, and cross-talk in the LSI devices. 5) Partial replacement of Si-O bond with Si-(CH x ) y and incorporation of pores into the matrix film are major ways to reduce the dielectric constant.…”

Section: Introductionmentioning

confidence: 99%

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Inoue

Furutake

Ito

et al. 2008

jjap

View full text Add to dashboard Cite

Impact of barrier metal sputtering on physical and chemical damages in the low-k SiOCH films is investigated. In RF sputtering system, the potential drop across the anode sheath accelerates the ion in the plasma toward the wafer surface, inducing damages in the low-k SiOCH dielectrics. High DC bias on the target reduces the anode sheath voltage to suppress the process-induced damage in the SiOCH films. For conventional rigid and porous SiOCH films with methyl (-CH 3 ) additives, the accelerated ions break the Si-CH 3 bond, pushing up the dielectric constants. A new type of SiOCH film such as a molecular-pore-stacking (MPS) SiOCH, which is consisted of hexagonal silica ring with a large amount of hydrocarbon groups surrounding the core silica structure, exhibits high endurance to the sputtering-induced damages. The long side-chains of the hydrocarbon prevent the direct ion bonberdment to the core Si-CH 3 bonds by sacrificing the C-C bond in the chains, keeping the low dielectric constant in the MPS SiOCH.

show abstract

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Cited by 11 publications

References 0 publications

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Effects of Low-k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Contact Info

Product

Resources

About