Effects of Low-k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Abstract

Low capacitance and highly reliable Cu dual-damascene (DD) interconnects have been developed with self-organized “seamless low-k SiOCH stacks” (SEALS) structure. A carbon-rich sub-nano porous SiOCH (k=2.5) was directly stacked on an oxygen-rich porous SiOCH (k=2.7) in the SEALS structure, without a hard-mask (HM) and etch-stop (ES) layer of SiO2. The effective k-value (k eff) of the Cu DD interconnect including the SiCN capping layer (k=4.9) was reduced to 2.9 compared to 3.4 on a conventional hybrid structure with SiO2-HM and ES, which had been used in 65-nm-node mass production. The interconnect delay of a 45-nm-node complementary metal oxide semiconductor (CMOS) ring oscillator (RO) was reduced by 15% referring to that of the conventional hybrid structure. Interconnect reliabilities, such as the interline time dependent dielectric breakdown (TDDB) and thermal cycles, were unchanged from those of the conventional hybrid interconnects. No failure was detected for chip package interaction (CPI) during reliability tests in a plastic ball grid array (PBGA) package. SEALS is a promising structure for scaled down ultra large scale integrations (ULSIs) for highly reliable and high speed operation, and low power consumption.