Highly reliable 50nm contact cell technology for 256Mb PRAM

Phase change memories: State-of-the-art, challenges and perspectives

“…Samsung, following the lance-like approach, has demonstrated 64 Mb arrays with MOSFET selectors, scaling progressively the reset current from the 2.0 mA in the 240 nm technology [7] to 600 lA at the 120 nm node with nitrogendoped GST [8]. By using a two-step CMP process a better control of the contact size (52 ± 7 nm) has been achieved and a further reduction of the programming current has been obtained limiting the TiN deposition only along the periphery of the lance [23].…”

Phase change memory

“…Usually, a very high current is required to generate an adequate energy to switch the cell, especially for RESET operations. To make PCM operate at CMOS compatible voltages, various cell structures have been developed to improve electrical-to-thermal efficiency through device geometry optimization [16,[22][23][24][25][26][27][28]. One effective approach has been to create sub-lithographic features to minimize the volume of the phase change material in the current path through the PCM storage element.…”

“…One effective approach has been to create sub-lithographic features to minimize the volume of the phase change material in the current path through the PCM storage element. Depending on the implementation of the sub-lithographic aperture, PCM cell structures can be divided into two categories ( Figure 4): 1) contact-minimized cells [22][23][24]; and 2) volume-minimized cells [16, 26-29, 31, 32]. Figure 5 shows a mushroom cell, which is a contact-minimized cell [23].…”

“…Depending on the implementation of the sub-lithographic aperture, PCM cell structures can be divided into two categories ( Figure 4): 1) contact-minimized cells [22][23][24]; and 2) volume-minimized cells [16, 26-29, 31, 32]. Figure 5 shows a mushroom cell, which is a contact-minimized cell [23]. The cross-sectional area between bottom electrical contact (BEC) and the phase change material layer is minimized to effectively confine the current to optimize heat generation.…”

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

“…Recently, some methods have been proposed to improve the reliability of PCRAM by studying the material characteristics and improving the fabrication process. S.J Ahn et al introduced a 2-step chemical mechanical polishing (CMP) process and a ring-shaped contact structure to achieve a highly reliable 50 nm contact cell technology for PCRAM applications [6]. C. Sandhya et al improved the chip reliability by carefully controlling the doping parameters on GeTe with Boron [7].…”