Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 &amp;amp;#x003BC;m&lt;sup&gt;2&lt;/sup&gt; Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

Park, Young-Woo; Choi, Jung Han; Kang, Chang Seok; Lee, Changhyun; Shin, Yuchoel; Choi, Bok Kyoung; Kim, Juhung; Jeon, Sanghun; Sel, Jongsun; Park, Jintaek; Choi, Kihwan; Yoo, Taehwa; Sim, Jaesung; Kim, Kinam

doi:10.1109/iedm.2006.346900

Cited by 55 publications

(43 citation statements)

References 2 publications

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“…Though there is a strong dependence on the position of the SiON interface layer, the erase state V FB shows negligible degradation for Si + /N + = 4/4 and 6/2 (nm) bi-layer device. This is in stark contrast to the single layer nitride endurance results in this study as well as in the literature [3], [6], [7], [16], [17] and consistent with recent results on NAN stacks [8] cycling endurance is worth a mention as the improvement is inexplicable by attribution to simply the ratio of Si + vs. N + nitride layer thickness in the bi-layer stack (as plausible in the case of W/E or retention performance). The signature effect of the SiON barrier layer explains the improvement for the bi-layer endurance as single layer nitride endurance is poor -regardless of the choice of nitride composition.…”

Section: Methodscontrasting

confidence: 56%

“…It has been shown that Conventional Floating Gate (FG) Flash is difficult to scale beyond the 3X node due to cell to cell interference, loss of Control Gate to FG coupling, reduction in FG volume (hence the number of electrons stored per bit) [2] and the inability to scale the tunnel oxide thickness below about 7-8nm [1]. Of all the possible alternatives, Charge Trap Flash (CTF) [3] is an attractive candidate as it exhibits negligible cell to cell interference, planar structure hence better scalability and fully CMOS compatible fabrication process. However, CTF suffers from conflicting trends in memory window versus data retention and needs careful attention before becoming a viable technology option.…”

Section: Introductionmentioning

confidence: 99%

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Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

Sandhya

Ganguly

Singh

et al. 2008

2008 IEEE International Reliability Physics Symposium

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The performance and reliability of Charge Trap Flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and Nrich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.

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Section: Methodscontrasting

confidence: 56%

Section: Introductionmentioning

confidence: 99%

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

Sandhya

Ganguly

Singh

et al. 2008

2008 IEEE International Reliability Physics Symposium

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“…Recently, however, the NAND Flash memory industry has faced the scaling limitation of the conventional floating gate (FG) NAND cell. For a promising solution as the alternative technology to replace FG flash memory, the charge trap type flash memory, like Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been focused since it provides simpler process steps than FG [3], lower cell-to-cell coupling [4], and virtual immunity to stress-induced leakage current (SILC) [5].…”

Section: Introductionmentioning

confidence: 99%

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Kim¹,

Yang²,

Kim³

et al. 2015

Transactions on Electrical and Electronic Materials

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This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) siliconoxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

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“…The term "localized" implies the charge storage in discrete storage nodes (Si 3 N 4 bulk traps in CTF and Fermi level of metal in NC) which are electrically isolated from each other. Ease of integration is the biggest factor in favor of the CTF devices [13]. So far, reported CTF devices have shown good memory window but poor retention [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

Singh

Bisht

Auluck

et al. 2010

IEEE Trans. Electron Devices

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Abstract-Memory window (MW) and the retention of singlelayer (SL) and dual-layer (DL) platinum (Pt) nanocrystal (NC) devices are extensively studied before and after program/erase (P/E) cycling. DL devices show better charge storage capability and reliability over the SL devices. Up to 50% improvement in the stored charge is estimated in the DL device over SL when P/E is performed at equal field. Excellent high temperature and postcycling retention capabilities of SL and DL devices are shown. The impact of the interlayer film (ILF) thickness on the retention of the DL structure is reported. While SL devices show poor P/E cycling endurance, DL cycling is shown to meet the minimum requirements of the multilevel cell (MLC) operation.

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Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 &#x003BC;m<sup>2</sup> Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

Cited by 55 publications

References 2 publications

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

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